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authorT.H. Lin <t.h_lin@quanta.corp-partner.google.com>2018-08-10 15:14:21 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-08-14 14:19:07 +0000
commit06fd881ed959fa8090c58d4848b2494ed19e75a8 (patch)
tree5ddc2105b6077f9d4c8673092cf415683b4f1187
parent0f3609b3a2d2d848921de30e704df379b195e6a1 (diff)
mb/google/poppy/variant/nami: Add TSR2 on DPTF
Add TSR2 DART/DTRT package BUG=b:110451144 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test image with dptf.dv Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
-rw-r--r--src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
index 614865aed8..2b3bd255a5 100644
--- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
@@ -41,6 +41,16 @@
#define DPTF_TSR1_ACTIVE_AC3 42
#define DPTF_TSR1_ACTIVE_AC4 39
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Thermal_Sensor_Remote_CPU"
+#define DPTF_TSR2_PASSIVE 75
+#define DPTF_TSR2_CRITICAL 125
+#define DPTF_TSR2_ACTIVE_AC0 50
+#define DPTF_TSR2_ACTIVE_AC1 47
+#define DPTF_TSR2_ACTIVE_AC2 45
+#define DPTF_TSR2_ACTIVE_AC3 42
+#define DPTF_TSR2_ACTIVE_AC4 39
+
#define DPTF_ENABLE_CHARGER
#define DPTF_ENABLE_FAN_CONTROL
@@ -91,6 +101,10 @@ Name (DART, Package () {
Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
0, 0, 0
+ },
+ Package () {
+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0,
+ 0, 0, 0
}
})
#endif
@@ -104,6 +118,9 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on TSR1 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on TSR2 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 1, 0, 0, 0, 0 },
})
Name (MPPC, Package ()