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authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-10-08 16:36:25 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-12 08:48:17 +0000
commit06c022f3a1c67fbe81be084f1a84f93f5be8842d (patch)
tree0b837ab06e1573f3ae30f9aece6269d7d5924788
parentcce822840d0514ae03fad029340202964bb1c59f (diff)
soc/intel/common/block/smm: Fix compilation without intel uart code
Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART. Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
-rw-r--r--src/soc/intel/common/block/smm/smihandler.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index ab88a51118..270b1aa796 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -200,8 +200,8 @@ void smihandler_southbridge_sleep(
break;
case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
-
- gnvs->uior = uart_is_controller_initialized();
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART))
+ gnvs->uior = uart_is_controller_initialized();
/* Invalidate the cache before going to S3 */
wbinvd();