diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-30 16:36:46 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-01 00:19:57 +0200 |
| commit | 0577a1e9d344e3c4617c58743380bdb8eb6ed2de (patch) | |
| tree | a07c4841697dddff36f8aacd07d4f94a1f29b313 | |
| parent | a795ae1392327a17d37193834271883743b21311 (diff) | |
mainboard/google/reef: support WLAN_PE_RST
The reef DVT build added another way to assert the wifi module's
reset line. Ensure it's deasserted by default. For previous boards
this GPIO doesn't matter because it wasn't routed anyway.
BUG=chrome-os-partner:56737
Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/google/reef/gpio.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index dbe70624da..09c1ee9355 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -271,7 +271,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_119, UP_20K, DEEP), /* SIO_SPI_2_FS0 */ PAD_CFG_GPI(GPIO_120, UP_20K, DEEP), /* SIO_SPI_2_FS1 */ PAD_CFG_GPI(GPIO_121, UP_20K, DEEP), /* SIO_SPI_2_FS2 */ - PAD_CFG_GPI(GPIO_122, UP_20K, DEEP), /* SIO_SPI_2_RXD */ + /* WLAN_PE_RST - default to deasserted. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* SIO_SPI_2_TXD */ /* Debug tracing. */ @@ -348,6 +349,8 @@ static const struct pad_config early_gpio_table[] = { /* I2C2 - TPM */ PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ + /* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ }; /* GPIO settings before entering sleep. */ |