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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-02-27 08:15:01 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-02-28 10:35:22 +0000 |
| commit | 035876c4ddb0c9cb92b867bc329f74f1021bf0f7 (patch) | |
| tree | 65320a3668d3c4346fc0d6638a36cf64f6e3cfbd | |
| parent | 7ba14406c30f90cebde9f539f1987348cfc998e4 (diff) | |
mb/intel/saddlebrook: Fix 2nd DIMM slot
Assumed broken during review and rebase. The
SPD at address 0x52 will appear at index 1.
Change-Id: I213853d2b981294554d8d1b254da476905a41c13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/mainboard/intel/saddlebrook/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 5b4732a8c7..d19629cf9e 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -56,7 +56,7 @@ void mainboard_memory_init_params( printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len); memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2]; + memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", memory_params->MemorySpdPtr00); printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", |