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authorJoey Peng <joey.peng@lcfc.corp-partner.google.com>2022-01-18 15:30:32 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-25 18:04:45 +0000
commit0251ecdd62e9ee8a1061f29e8fc307a4109505da (patch)
treef6019ebb72abe3760d36dedefa801de55b23a0a7
parent52ac424b9cd2fa7ea7c3e4de90c847b22c1aee4b (diff)
mb/google/brya/var/taniks: Run time probe for NVMe SSD and MMC
Taniks will use two PCIE port signals with one slot, one CLK and one CLKREQ at next build. In order to accommodate this, probe statements are added to the devicetree. This only affects NVME SSD and EMMC. BUG=b:215040000 TEST=Build FSP with debug output enabled, and observe the correct root ports being initialized depending on the FW_CONFIG values for BOOT_EMMC and BOOT_NVME. Cq-Depend:chromium:3397561 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
-rw-r--r--src/mainboard/google/brya/variants/taniks/overridetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb
index ab98312628..96d4ad5ed7 100644
--- a/src/mainboard/google/brya/variants/taniks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb
@@ -223,6 +223,7 @@ chip soc/intel/alderlake
.clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
+ probe BOOT_NVME_MASK BOOT_NVME_ENABLED
end
device ref tbt_pcie_rp0 off end
device ref tbt_pcie_rp1 off end
@@ -345,6 +346,23 @@ chip soc/intel/alderlake
end
end
end
+ device ref pcie_rp9 on
+ # Enable NVMe PCIE 9 using clk 0
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 0,
+ .clk_req = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+ register "srcclk_pin" = "0"
+ device generic 0 on
+ probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
+ end
+ end
+ probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
+ end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]