diff options
| author | JingleHsuWiwynn <jingle_hsu@wiwynn.com> | 2021-10-07 10:45:47 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-11-10 19:06:41 +0000 |
| commit | 014901bd9bd3df7ee919de228969f0359db0de4f (patch) | |
| tree | 9f207b7f773772131228f22d17b22e3ef4222d17 | |
| parent | 323e5a84eb53c35ed9b58fb7e5045cc8b7c42986 (diff) | |
soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard
to soc
Move SMBIOS type 4 override functions from mainboard to soc so that all
xeon family cpus share same functions without implementing again.
Tested=On OCP Deltalake, dmidecode -t 4 shows expected info.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/ocp/deltalake/ramstage.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/ramstage.c | 11 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index fb81e10962..0fca9207f2 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -327,17 +327,6 @@ void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 t->bank_locator = smbios_add_string(t->eos, buf); } -unsigned int smbios_processor_family(struct cpuid_result res) -{ - return 0xb3; /* Xeon */ -} - -unsigned int smbios_processor_characteristics(void) -{ - /* 64-bit Capable, Multi-Core, Power/Performance Control */ - return 0x8c; /* BIT2 | BIT3 | BIT7 */ -} - static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings; diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c index 68d5d4658c..9882660b16 100644 --- a/src/soc/intel/xeon_sp/ramstage.c +++ b/src/soc/intel/xeon_sp/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/cpu.h> #include <smbios.h> unsigned int smbios_cache_error_correction_type(u8 level) @@ -24,3 +25,13 @@ unsigned int smbios_cache_conf_operation_mode(u8 level) return SMBIOS_CACHE_OP_MODE_UNKNOWN; } } + +unsigned int smbios_processor_family(struct cpuid_result res) +{ + return SMBIOS_PROCESSOR_FAMILY_XEON; +} + +unsigned int smbios_processor_characteristics(void) +{ + return PROCESSOR_64BIT_CAPABLE|PROCESSOR_MULTI_CORE|PROCESSOR_POWER_PERFORMANCE_CONTROL; +} |