mb/google/zork: Fix pad configurations for wake signals

This change updates the pad configurations for wake lines as
follows:
1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake
using GPIO controller block. This is because pen eject signal is not
dual routed and the trigger filtering is set by the kernel driver
differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and
instead has to fall back to using GPIO controller wake.
2. All other wake signals (EC, trackpad, fingerprint) need to be
configured as SCI. This allows OS to enable/disable wake from these
sources if required. Example: powerd disables wake from trackpad when
in tablet mode. Hence, all other wake sources use SCI.

BUG=b:159832123
TEST=Verified wake using pen eject and EC.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42951
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 8 insertions, 10 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index 711a94cb10..75a7096cc2 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -13,7 +13,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
 	/* PEN_POWER_EN - reset */
 	PAD_GPO(GPIO_5, LOW),
 	/* EC_FCH_WAKE_L */
-	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
+	PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
 	/* PCIE_RST1_L - Variable timings (May remove) */
 	PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
 	/* NVME_AUX_RESET_L */
@@ -46,7 +46,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
 	/* EN_PWR_TOUCHPAD_PS2 - reset */
 	PAD_GPO(GPIO_6, LOW),
 	/* EC_FCH_WAKE_L */
-	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
+	PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
 	/* PCIE_RST1_L - Variable timings (May remove) */
 	PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
 	/* NVME_AUX_RESET_L */
@@ -80,7 +80,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* PCIE_WAKE_L */
 	PAD_NF(GPIO_2, WAKE_L, PULL_UP),
 	/* PEN_DETECT_ODL */
-	PAD_GPI(GPIO_4, PULL_UP),
+	PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3),
 	/* PEN_POWER_EN - Enabled*/
 	PAD_GPO(GPIO_5, HIGH),
 	/* EN_PWR_TOUCHPAD */
@@ -90,8 +90,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* I2S_LRCLK - Bit banged in depthcharge */
 	PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
 	/* TOUCHPAD_INT_ODL */
-	/* TODO: Make sure driver sets as wake source */
-	PAD_GPI(GPIO_9, PULL_UP),
+	PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
 	/* S0iX SLP - (unused - goes to EC & FPMCU */
 	PAD_GPI(GPIO_10, PULL_UP),
 	/* EC_IN_RW_OD */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index f7e30ef305..4fbc4f0715 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -13,7 +13,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
 	/* PEN_POWER_EN - reset */
 	PAD_GPO(GPIO_5, LOW),
 	/* EC_FCH_WAKE_L */
-	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
+	PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
 	/* NVME_AUX_RESET_L */
 	PAD_GPO(GPIO_40, HIGH),
 	/* EN_PWR_TOUCHPAD_PS2 - reset */
@@ -42,7 +42,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
 	/* EN_PWR_TOUCHPAD_PS2 - reset */
 	PAD_GPO(GPIO_13, LOW),
 	/* EC_FCH_WAKE_L */
-	PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
+	PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
 	/* NVME_AUX_RESET_L */
 	PAD_GPO(GPIO_40, HIGH),
 	/* EMMC_RESET - reset (default stuffing unused)*/
@@ -76,14 +76,13 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
 	/* PEN_POWER_EN - Enabled*/
 	PAD_GPO(GPIO_5, HIGH),
 	/* FPMCU_INT_L */
-	PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5),
+	PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW),
 	/* I2S_SDIN */
 	PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
 	/* I2S_LRCLK - Bit banged in depthcharge */
 	PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
 	/* TOUCHPAD_INT_ODL */
-	/* TODO: Make sure driver sets as wake source */
-	PAD_GPI(GPIO_9, PULL_UP),
+	PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
 	/* S0iX SLP - (unused - goes to EC & FPMCU */
 	PAD_GPI(GPIO_10, PULL_UP),
 	/* FPMCU_RST_L */