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authorNaveen Krishna Chatradhi <naveenkrishna.ch@intel.com>2015-07-10 17:09:37 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-07-21 20:23:25 +0200
commitf82758a8762ffb1df8fafed5769dfbbd63cc216e (patch)
treed2c326ae14f3a0abda1918f89da8ecf9212aa345
parent75154b801f8c31298125d4fc0a3ee069058dc0b6 (diff)
Glados: Update Serial IO modes in devicetree
This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/mainboard/google/glados/devicetree.cb2
-rw-r--r--src/soc/intel/skylake/Kconfig1
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 206086667b..6f89063ffb 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,7 +16,7 @@ chip soc/intel/skylake
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoPci, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
- [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
+ [PchSerialIoIndexUart2] = PchSerialIoPci, \
}"
# Enable Root port 1 and 5.
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 856b84fa1f..dbf68a737d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_ROM
select CAR_MIGRATION
select CONSOLE_SERIAL8250MEM
+ select CONSOLE_SERIAL8250MEM_32
select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_MICROCODE_IN_CBFS