diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-11-02 09:19:43 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-14 18:23:05 +0100 |
| commit | f72ad02158945c0c80aedd81218fb4fc4080cf1e (patch) | |
| tree | 4c62fdbf903dd07b38abc98b54b0cfe7a3999fee | |
| parent | 4412bc4ae8f8ab33a49cdd00098754ff7c333a01 (diff) | |
graysreef: update platform information
Some of the Lynx Point ids were off. Correct those and make
the pei data BAR fields consistent with the others.
Change-Id: I4102439588362cdb94643bd1ce69c9fa4278329e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2622
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/mainboard/intel/graysreef/romstage.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/report_platform.c | 9 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c index 2431d946f2..c12e03c7e4 100644 --- a/src/mainboard/intel/graysreef/romstage.c +++ b/src/mainboard/intel/graysreef/romstage.c @@ -135,7 +135,7 @@ void main(unsigned long bist) mchbar: DEFAULT_MCHBAR, dmibar: DEFAULT_DMIBAR, epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, + pciexbar: DEFAULT_PCIEXBAR, smbusbar: SMBUS_IO_BASE, wdbbar: 0x4000000, wdbsize: 0x1000, diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 6db8ae09a3..9a141b6940 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -74,10 +74,11 @@ static struct { } pch_table [] = { {0x8c41, "Mobile Engineering Sample"}, {0x8c42, "Desktop Engineering Sample"}, - {0x8c46, "Z87"}, - {0x8c49, "Z85"}, - {0x8c4a, "HM86"}, - {0x8c4b, "H87"}, + {0x8c44, "Z87"}, + {0x8c46, "Z85"}, + {0x8c49, "HM86"}, + {0x8c4a, "H87"}, + {0x8c4b, "HM87"}, {0x8c4c, "Q85"}, {0x8c4e, "Q87"}, {0x8c4f, "QM87"}, |