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authorAngel Pons <th3fanbus@gmail.com>2020-10-23 11:24:07 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-10-24 21:43:10 +0000
commitebf800c538f45c406838dbd0746b5a387d01fc3b (patch)
tree42e496761ab35ad82f2cca9a3d31d26311901f26
parentf27662f5baa4367e555aa180c02846543a6b5692 (diff)
nb/intel/haswell/early_init.c: Remove invalid register writes
MRC does not use the value of SSKPD, and will overwrite it with constant values at the end of memory initialisation. Since coreboot does not rely on this particular bit's value, it is safe to drop the writes to set it. MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any documentation or code I have access to; not even for Sandy/Ivy Bridge, the platform where this mysterious register write originally came from. These workarounds were copied from Sandy Bridge, but do not apply to Haswell. They were dropped on Broadwell, so drop them for Haswell too. Tested on Asrock B85M Pro4, still boots. Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/northbridge/intel/haswell/early_init.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 79cc27724c..a0e4211f02 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -146,16 +146,6 @@ static void haswell_setup_misc(void)
reg32 = MCHBAR32(SAPMCTL);
MCHBAR32(SAPMCTL) = reg32 | 1;
- /* GPU RC6 workaround for sighting 366252 */
- reg32 = MCHBAR32(SSKPD + 4);
- reg32 |= (1UL << 31);
- MCHBAR32(SSKPD + 4) = reg32;
-
- /* VLW (Virtual Legacy Wire?) */
- reg32 = MCHBAR32(0x6120);
- reg32 &= ~(1 << 0);
- MCHBAR32(0x6120) = reg32;
-
reg32 = MCHBAR32(INTRDIRCTL);
reg32 |= (1 << 4) | (1 << 5);
MCHBAR32(INTRDIRCTL) = reg32;