diff options
| author | Nils Jacobs <njacobs8@adsltotaal.nl> | 2012-01-09 20:27:07 +0100 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2012-01-09 23:50:26 +0100 |
| commit | eb84f6a978147fbe543fbe15af254632f215098a (patch) | |
| tree | 842ab50525eb21f7d719d61348c6ff59956ffd5d | |
| parent | 8d846135ff0779b19eccef0bbb15ddfe366205c6 (diff) | |
Fix Geode GX2 + LX caching for tiny bootblock.
Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>
| -rw-r--r-- | src/cpu/amd/model_lx/msrinit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c index 9c6e98e14c..11182501c1 100644 --- a/src/cpu/amd/model_lx/msrinit.c +++ b/src/cpu/amd/model_lx/msrinit.c @@ -22,10 +22,10 @@ static const msrinit_t msr_table[] = { - {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. + {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB. * Rom Properties: Write Serialize, WriteProtect. * RomBase: 0xFFFC0 - * SysTop to RomBase Properties: Write Serialize, Cache Disable. + * SysTop to RomBase Properties: Write Back. * SysTop: 0x000A0 * System Memory Properties: (Write Back) */ {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ |