diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-21 15:37:55 +0300 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-22 20:48:08 +0200 |
| commit | eac00d2dbbe57e10a130ea1c0c6d943c2a9f19c1 (patch) | |
| tree | 58f823cb824536080e618f85b819b364121abb8f | |
| parent | 7f5897a1c5bcd6062169368b827975faa9feeebf (diff) | |
intel/sandybridge: Locate CBMEM TOC early in ramstage
This patch allows the use of migrated CAR_GLOBAL variables from
the very beginning of ramstage. Without the patch, CAR_GLOBALS were
not available until northbridge set_resources().
Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3513
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0a413b4c7b..d8e2e9d6b3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,6 +51,21 @@ int bridge_silicon_revision(void) return bridge_revision_id; } +static unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); + return (unsigned long) tom; +} + +struct cbmem_entry *get_cbmem_toc(void) +{ + static struct cbmem_entry *toc = NULL; + if (!toc) + toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); + return toc; +} + /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA |