soc/intel/jasperlake: Update reserved GPIO names in gpio_soc_defs.h

Multiple GPIOs were defined as a reserved GPIO in JasperLake. Correcting
this GPIOs with proper name to align with EDS volume 2

Also removing unused GPIOs at the end of community 4 (group E).
Since those reserved GPIOs are at the end of the community, it won't
affect the offset calculations within community. This change will also
help us aligning pad numbering with kernel pin-ctrl drivers too.

Reference: DOC#618876 (EDS volume 2)

BUG=None
BRANCH=None
TEST=Platform boots fine and basic functionality such as SD, Wifi works.

Change-Id: I8326b7181d47a177261656f51602638d8ce80fbb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 132 insertions, 146 deletions

diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c
index 52c147fb04..2f13015534 100644
--- a/src/soc/intel/jasperlake/gpio.c
+++ b/src/soc/intel/jasperlake/gpio.c
@@ -34,10 +34,10 @@ static const struct reset_mapping rst_map_com0[] = {
 static const struct pad_group jsl_community0_groups[] = {
 
 	INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 0),	/* GPP_F */
-	INTEL_GPP(GPP_F0, GPIO_RSVD_0, GPIO_RSVD_8),
+	INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK),
 	INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32),	/* GPP_B */
-	INTEL_GPP(GPP_F0, GPIO_RSVD_9, GPIO_RSVD_10),
-	INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64),	/* GPP_A */
+	INTEL_GPP(GPP_F0, GPIO_GSPI0_CLK_LOOPBK, GPIO_GSPI1_CLK_LOOPBK),
+	INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_ESPI_CLK_LOOPBK, 64),	/* GPP_A */
 	INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96),	/* GPP_S */
 	INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128),	/* GPP_R */
 };
@@ -45,7 +45,7 @@ static const struct pad_group jsl_community0_groups[] = {
 static const struct pad_group jsl_community1_groups[] = {
 	INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160),		/* GPP_H */
 	INTEL_GPP_BASE(GPP_H0, GPP_D0, GPP_D23, 192),	/* GPP_D */
-	INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13),
+	INTEL_GPP(GPP_H0, GPIO_GSPI2_CLK_LOOPBK, GPIO_SPI1_CLK_LOOPBK),
 	INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224),		/* VGPIO */
 	INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256),		/* GPP_C */
 };
@@ -53,13 +53,12 @@ static const struct pad_group jsl_community1_groups[] = {
 /* This community is not visible to the OS */
 static const struct pad_group jsl_community2_groups[] = {
 	INTEL_GPP(GPD0, GPD0, GPD10),				/* GPD */
-	INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17),
+	INTEL_GPP(GPD0, GPIO_INPUT3VSEL, GPIO_DRAM_RESETB),
 };
 
 static const struct pad_group jsl_community4_groups[] = {
-	INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23),
-	INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288),		/* GPP_E */
-	INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36),
+	INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_MLK_RSTB),
+	INTEL_GPP_BASE(GPIO_L_BKLTEN, GPP_E0, GPP_E23, 288),		/* GPP_E */
 };
 
 static const struct pad_group jsl_community5_groups[] = {
@@ -70,8 +69,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
 	/* GPP F, B, A, S, R */
 	[COMM_0] = {
 		.port = PID_GPIOCOM0,
-		.first_pad = GPP_F0,
-		.last_pad = GPP_R7,
+		.first_pad = GPIO_COM0_START,
+		.last_pad = GPIO_COM0_END,
 		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -90,8 +89,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
 	/* GPP H, D, VGPIO, C */
 	[COMM_1] = {
 		.port = PID_GPIOCOM1,
-		.first_pad = GPP_H0,
-		.last_pad = GPP_C23,
+		.first_pad = GPIO_COM1_START,
+		.last_pad = GPIO_COM1_END,
 		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -110,8 +109,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
 	/* GPD */
 	[COMM_2] = {
 		.port = PID_GPIOCOM2,
-		.first_pad = GPD0,
-		.last_pad = GPIO_RSVD_17,
+		.first_pad = GPIO_COM2_START,
+		.last_pad = GPIO_COM2_END,
 		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -130,8 +129,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
 	/* GPP E */
 	[COMM_4] = {
 		.port = PID_GPIOCOM4,
-		.first_pad = GPIO_RSVD_18,
-		.last_pad = GPIO_RSVD_36,
+		.first_pad = GPIO_COM4_START,
+		.last_pad = GPIO_COM4_END,
 		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -150,8 +149,8 @@ static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
 	/* GPP G */
 	[COMM_5] = {
 		.port = PID_GPIOCOM5,
-		.first_pad = GPP_G0,
-		.last_pad = GPP_G7,
+		.first_pad = GPIO_COM5_START,
+		.last_pad = GPIO_COM5_END,
 		.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
index 8d6064c8f7..25a0625842 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h
@@ -53,64 +53,64 @@
 #define GPP_F19		19
 
 /* Group B */
-#define GPIO_RSVD_0	20
-#define GPIO_RSVD_1	21
-#define GPIO_RSVD_2	22
-#define GPIO_RSVD_3	23
-#define GPIO_RSVD_4	24
-#define GPIO_RSVD_5	25
-#define GPIO_RSVD_6	26
-#define GPIO_RSVD_7	27
-#define GPIO_RSVD_8	28
-#define GPP_B0		29
-#define GPP_B1		30
-#define GPP_B2		31
-#define GPP_B3		32
-#define GPP_B4		33
-#define GPP_B5		34
-#define GPP_B6		35
-#define GPP_B7		36
-#define GPP_B8		37
-#define GPP_B9		38
-#define GPP_B10		39
-#define GPP_B11		40
-#define GPP_B12		41
-#define GPP_B13		42
-#define GPP_B14		43
-#define GPP_B15		44
-#define GPP_B16		45
-#define GPP_B17		46
-#define GPP_B18		47
-#define GPP_B19		48
-#define GPP_B20		49
-#define GPP_B21		50
-#define GPP_B22		51
-#define GPP_B23		52
-#define GPIO_RSVD_9	53
-#define GPIO_RSVD_10	54
+#define GPIO_SPI0_IO_2		20
+#define GPIO_SPI0_IO_3		21
+#define GPIO_SPI0_MOSI_IO_0	22
+#define GPIO_SPI0_MOSI_IO_1	23
+#define GPIO_SPI0_TPM_CSB	24
+#define GPIO_SPI0_FLASH_0_CSB	25
+#define GPIO_SPI0_FLASH_1_CSB	26
+#define GPIO_SPI0_CLK		27
+#define GPIO_SPI0_CLK_LOOPBK	28
+#define GPP_B0			29
+#define GPP_B1			30
+#define GPP_B2			31
+#define GPP_B3			32
+#define GPP_B4			33
+#define GPP_B5			34
+#define GPP_B6			35
+#define GPP_B7			36
+#define GPP_B8			37
+#define GPP_B9			38
+#define GPP_B10			39
+#define GPP_B11			40
+#define GPP_B12			41
+#define GPP_B13			42
+#define GPP_B14			43
+#define GPP_B15			44
+#define GPP_B16			45
+#define GPP_B17			46
+#define GPP_B18			47
+#define GPP_B19			48
+#define GPP_B20			49
+#define GPP_B21			50
+#define GPP_B22			51
+#define GPP_B23			52
+#define GPIO_GSPI0_CLK_LOOPBK	53
+#define GPIO_GSPI1_CLK_LOOPBK	54
 
 /* Group A */
-#define GPP_A0		55
-#define GPP_A1		56
-#define GPP_A2		57
-#define GPP_A3		58
-#define GPP_A4		59
-#define GPP_A5		60
-#define GPP_A6		61
-#define GPP_A7		62
-#define GPP_A8		63
-#define GPP_A9		64
-#define GPP_A10		65
-#define GPP_A11		66
-#define GPP_A12		67
-#define GPP_A13		68
-#define GPP_A14		69
-#define GPP_A15		70
-#define GPP_A16		71
-#define GPP_A17		72
-#define GPP_A18		73
-#define GPP_A19		74
-#define GPIO_RSVD_11	75
+#define GPP_A0			55
+#define GPP_A1			56
+#define GPP_A2			57
+#define GPP_A3			58
+#define GPP_A4			59
+#define GPP_A5			60
+#define GPP_A6			61
+#define GPP_A7			62
+#define GPP_A8			63
+#define GPP_A9			64
+#define GPP_A10			65
+#define GPP_A11			66
+#define GPP_A12			67
+#define GPP_A13			68
+#define GPP_A14			69
+#define GPP_A15			70
+#define GPP_A16			71
+#define GPP_A17			72
+#define GPP_A18			73
+#define GPP_A19			74
+#define GPIO_ESPI_CLK_LOOPBK	75
 
 /* Group S */
 #define GPP_S0		76
@@ -163,32 +163,32 @@
 #define GPP_H23		115
 
 /* Group D */
-#define GPP_D0		116
-#define GPP_D1		117
-#define GPP_D2		118
-#define GPP_D3		119
-#define GPP_D4		120
-#define GPP_D5		121
-#define GPP_D6		122
-#define GPP_D7		123
-#define GPP_D8		124
-#define GPP_D9		125
-#define GPP_D10		126
-#define GPP_D11		127
-#define GPP_D12		128
-#define GPP_D13		129
-#define GPP_D14		130
-#define GPP_D15		131
-#define GPP_D16		132
-#define GPP_D17		133
-#define GPP_D18		134
-#define GPP_D19		135
-#define GPP_D20		136
-#define GPP_D21		137
-#define GPP_D22		138
-#define GPP_D23		139
-#define GPIO_RSVD_12	140
-#define GPIO_RSVD_13	141
+#define GPP_D0			116
+#define GPP_D1			117
+#define GPP_D2			118
+#define GPP_D3			119
+#define GPP_D4			120
+#define GPP_D5			121
+#define GPP_D6			122
+#define GPP_D7			123
+#define GPP_D8			124
+#define GPP_D9			125
+#define GPP_D10			126
+#define GPP_D11			127
+#define GPP_D12			128
+#define GPP_D13			129
+#define GPP_D14			130
+#define GPP_D15			131
+#define GPP_D16			132
+#define GPP_D17			133
+#define GPP_D18			134
+#define GPP_D19			135
+#define GPP_D20			136
+#define GPP_D21			137
+#define GPP_D22			138
+#define GPP_D23			139
+#define GPIO_GSPI2_CLK_LOOPBK	140
+#define GPIO_SPI1_CLK_LOOPBK	141
 
 /* Group VGPIO */
 #define VGPIO_0		142
@@ -252,33 +252,33 @@
 #define NUM_GPIO_COM1_PADS	(GPIO_COM1_END - GPIO_COM1_START + 1)
 
 /* Group GPD */
-#define GPD0		195
-#define GPD1		196
-#define GPD2		197
-#define GPD3		198
-#define GPD4		199
-#define GPD5		200
-#define GPD6		201
-#define GPD7		202
-#define GPD8		203
-#define GPD9		204
-#define GPD10		205
-#define GPIO_RSVD_14	206
-#define GPIO_RSVD_15	207
-#define GPIO_RSVD_16	208
-#define GPIO_RSVD_17	209
+#define GPD0			195
+#define GPD1			196
+#define GPD2			197
+#define GPD3			198
+#define GPD4			199
+#define GPD5			200
+#define GPD6			201
+#define GPD7			202
+#define GPD8			203
+#define GPD9			204
+#define GPD10			205
+#define GPIO_INPUT3VSEL		206
+#define GPIO_SLP_SUSB		207
+#define GPIO_WAKEB		208
+#define GPIO_DRAM_RESETB	209
 
 #define GPIO_COM2_START		GPD0
-#define GPIO_COM2_END		GPIO_RSVD_17
+#define GPIO_COM2_END		GPIO_DRAM_RESETB
 #define NUM_GPIO_COM2_PADS	(GPIO_COM2_END - GPIO_COM2_START + 1)
 
 /* Group E */
-#define GPIO_RSVD_18	210
-#define GPIO_RSVD_19	211
-#define GPIO_RSVD_20	212
-#define GPIO_RSVD_21	213
-#define GPIO_RSVD_22	214
-#define GPIO_RSVD_23	215
+#define GPIO_L_BKLTEN	210
+#define GPIO_L_BKLTCTL	211
+#define GPIO_L_VDDEN	212
+#define GPIO_SYS_PWROK	213
+#define GPIO_SYS_RESETB	214
+#define GPIO_MLK_RSTB	215
 #define GPP_E0		216
 #define GPP_E1		217
 #define GPP_E2		218
@@ -303,39 +303,26 @@
 #define GPP_E21		237
 #define GPP_E22		238
 #define GPP_E23		239
-#define GPIO_RSVD_24	240
-#define GPIO_RSVD_25	241
-#define GPIO_RSVD_26	242
-#define GPIO_RSVD_27	243
-#define GPIO_RSVD_28	244
-#define GPIO_RSVD_29	245
-#define GPIO_RSVD_30	246
-#define GPIO_RSVD_31	247
-#define GPIO_RSVD_32	248
-#define GPIO_RSVD_33	249
-#define GPIO_RSVD_34	250
-#define GPIO_RSVD_35	251
-#define GPIO_RSVD_36	252
 
-#define GPIO_COM4_START		GPIO_RSVD_18
-#define GPIO_COM4_END		GPIO_RSVD_36
+#define GPIO_COM4_START		GPIO_L_BKLTEN
+#define GPIO_COM4_END		GPP_E23
 #define NUM_GPIO_COM4_PADS	(GPIO_COM4_END - GPIO_COM4_START + 1)
 
 /* Group G */
-#define GPP_G0		253
-#define GPP_G1		254
-#define GPP_G2		255
-#define GPP_G3		256
-#define GPP_G4		257
-#define GPP_G5		258
-#define GPP_G6		259
-#define GPP_G7		260
+#define GPP_G0		240
+#define GPP_G1		241
+#define GPP_G2		242
+#define GPP_G3		243
+#define GPP_G4		244
+#define GPP_G5		245
+#define GPP_G6		246
+#define GPP_G7		247
 
 #define GPIO_COM5_START		GPP_G0
 #define GPIO_COM5_END		GPP_G7
 #define NUM_GPIO_COM5_PADS	(GPIO_COM5_END - GPIO_COM5_START + 1)
 
-#define TOTAL_PADS	261
+#define TOTAL_PADS	248
 
 #define COMM_0		0
 #define COMM_1		1