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authorAaron Durbin <adurbin@chromium.org>2017-08-17 17:04:08 -0600
committerAaron Durbin <adurbin@chromium.org>2017-08-21 16:00:40 +0000
commitd6bd825d6c584d38bb69e5c4cccae4255837f359 (patch)
tree3ce6c5a60c634085753ee84e1a26a7acfe685ddb
parentf771de445d6538d049f36c8522b9f42e8dd9c858 (diff)
soc/intel/apollolake: remove duplicate gpio GPE defines
Remove the duplicate MISCCFG_GPE0_DW* macros that are already present in the common gpio code. Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/soc/intel/apollolake/include/soc/gpio_glk.h7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h
index 0253981064..b9a219ee06 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_glk.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h
@@ -276,13 +276,6 @@
#define GPIO_MAX_NUM_PER_GROUP 32
-#define MISCCFG_GPE0_DW0_SHIFT 8
-#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
-#define MISCCFG_GPE0_DW1_SHIFT 12
-#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
-#define MISCCFG_GPE0_DW2_SHIFT 16
-#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
-
/* Host Software Pad Ownership Register.
* The pins in the community are divided into 3 groups :
* GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95