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authorJamie Ryu <jamie.m.ryu@intel.com>2020-07-23 19:00:52 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-08-30 22:06:39 +0000
commitd10a10befd7046e50c72903ac8799e81d5f52a20 (patch)
tree5fd825996b711c0c2d6d8d3101be573ba03704ae
parentf0b6b30c46049e9849474965c87c83e7540e25dc (diff)
mb/google/volteer: Update flashmap descriptor for CSE Lite FW update
To support CSE Lite firmware update, CSE RW partition is extracted from CSE blob binary and added to FW_MAIN_A and FW_MAIN_B. CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and FW_MAIN_B is increased to avoid an overflow. BUG=b:140448618 TEST=build with me_rw binary blob for volteer and boot to kernel. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/volteer/chromeos.fmd14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd
index 60ea3ded64..07a5464068 100644
--- a/src/mainboard/google/volteer/chromeos.fmd
+++ b/src/mainboard/google/volteer/chromeos.fmd
@@ -7,16 +7,16 @@ FLASH@0xfe000000 0x2000000 {
# Place RW_LEGACY at the start of BIOS region such that the rest
# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
# SPI flash only the top 16MiB actually gets memory mapped.
- RW_LEGACY(CBFS)@0x0 0xf00000
- RW_SECTION_A@0xf00000 0x3e0000 {
+ RW_LEGACY(CBFS)@0x0 0xb00000
+ RW_SECTION_A@0xb00000 0x5e0000 {
VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x3cffc0
- RW_FWID_A@0x3dffc0 0x40
+ FW_MAIN_A(CBFS)@0x10000 0x5cffc0
+ RW_FWID_A@0x5dffc0 0x40
}
- RW_SECTION_B@0x12e0000 0x3e0000 {
+ RW_SECTION_B@0x10e0000 0x5e0000 {
VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x3cffc0
- RW_FWID_B@0x3dffc0 0x40
+ FW_MAIN_B(CBFS)@0x10000 0x5cffc0
+ RW_FWID_B@0x5dffc0 0x40
}
RW_MISC@0x16c0000 0x40000 {
UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {