diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-07 17:53:38 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-11 18:19:39 +0000 |
| commit | cca50852febd43817a961ca153c4e2ac3ec22a1b (patch) | |
| tree | ba131961be5b1e3a01a0f6cef608c7623217ceaa | |
| parent | 09564fce556558dfe9c14dd756513545ffeb1914 (diff) | |
soc/intel/skylake: Make use of Intel SPI common block
TEST=Build and boot soraka/eve
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3
Reviewed-on: https://review.coreboot.org/22361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/spi.c | 53 |
3 files changed, 3 insertions, 52 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f9431701a1..f66065a28d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -73,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index bc53922670..da45ec54a2 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -77,7 +77,6 @@ smm-y += gpio.c smm-y += pch.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c smm-y += uart.c diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index de0ff1317b..020994dbe8 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2016 Google Inc. + * Copyright 2017 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,17 +15,8 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/spi.h> -#include <intelblocks/fast_spi.h> -#include <intelblocks/gspi.h> #include <intelblocks/spi.h> -#include <soc/ramstage.h> -#include <spi-generic.h> +#include <soc/pci_devs.h> int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -51,44 +43,3 @@ int spi_soc_bus_to_devfn(unsigned int bus) } return -1; } - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, -#if !ENV_SMM - { .ctrlr = &gspi_ctrlr, .bus_start = 1, - .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)}, -#endif -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); - -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) - -static int spi_dev_to_bus(struct device *dev) -{ - return spi_soc_devfn_to_bus(dev->path.pci.devfn); -} - -static struct spi_bus_operations spi_bus_ops = { - .dev_to_bus = &spi_dev_to_bus, -}; - -static struct device_operations spi_dev_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_generic_bus, - .ops_pci = &soc_pci_ops, - .ops_spi_bus = &spi_bus_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d24, 0x9d29, 0x9d2a, 0 -}; - -static const struct pci_driver pch_spi __pci_driver = { - .ops = &spi_dev_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -#endif |