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authorDuncan Laurie <dlaurie@chromium.org>2015-01-14 17:30:20 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 20:14:33 +0200
commitcad2b7b6e896ffd11d09f0017da1fd1f80d61c09 (patch)
tree6f81f87cee70ce2edcbb5e635b44b2a51a8c9980
parentcf544ac1f9a62cc58e3911c23a0b905950a0ff2f (diff)
broadwell: Skip steps when disabling PCIe port
When disabling PCIe ports skip steps if no card is detected. This prevents the loop from timing out on each empty slot. BUG=chrome-os-partner:31424 BRANCH=broadwell TEST=build and boot on samus, check that this code is no longer timing out when disabling PCIe ports Change-Id: I84ee0e0e325784b3af06abe70420c07cf6e13ed2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4d759e2350dd00ceb7df196ac7008729dc1e4cef Original-Change-Id: Idd88f0f1191a5465a0d8dcca07b5c3a5c5ca8855 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240851 Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9489 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/soc/intel/broadwell/pcie.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 4476fe4f65..e217149bd3 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -321,12 +321,12 @@ static void root_port_commit_config(void)
do {
reg32 = pci_read_config32(dev, 0x328);
n++;
- if (((reg32 & 0xff000000) == 0x01000000) || (n > 500))
+ if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
break;
udelay(100);
} while (1);
- if (n > 500)
+ if (n > 50)
printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
dev_path(dev));