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authorMarc Jones <marc.jones@amd.com>2007-05-04 18:24:55 +0000
committerStefan Reinauer <stepan@openbios.org>2007-05-04 18:24:55 +0000
commitbc8176c5526ec9124aa99559f9432210be364dfe (patch)
treef4855271c5e16a2b9fba7d558a965c497a60e0cc
parent5941c25fe8e2118c93ef695ea3b30b65e016cdc1 (diff)
This patch adds support for the AMD Geode LX CPU. (rediffed)
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat
-rw-r--r--src/cpu/amd/model_lx/cache_as_ram.inc370
-rw-r--r--src/cpu/amd/model_lx/cpubug.c336
-rw-r--r--src/cpu/amd/model_lx/cpureginit.c431
-rw-r--r--src/cpu/amd/model_lx/model_lx_init.c3
-rw-r--r--src/cpu/amd/model_lx/syspreinit.c6
-rw-r--r--src/cpu/amd/model_lx/vsmsetup.c11
-rw-r--r--src/include/cpu/amd/geode_post_code.h196
-rw-r--r--src/include/cpu/amd/lxdef.h1040
-rw-r--r--src/include/cpu/amd/vr.h52
-rw-r--r--src/include/spd.h11
10 files changed, 1069 insertions, 1387 deletions
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
new file mode 100644
index 0000000000..fa90c5bf7f
--- /dev/null
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -0,0 +1,370 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+
+#define LX_STACK_BASE DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define LX_STACK_END LX_STACK_BASE+(DCACHE_RAM_SIZE-1)
+
+#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
+#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
+#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
+#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
+#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
+#include <cpu/amd/lxdef.h>
+/***************************************************************************
+/**
+/** DCacheSetup
+/**
+/** Setup data cache for use as RAM for a stack.
+/**
+/***************************************************************************/
+DCacheSetup:
+
+ invd
+ /* set cache properties */
+ movl $CPU_RCONF_DEFAULT, %ecx
+ rdmsr
+ movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
+ wrmsr
+
+ /* in LX DCDIS is set after POR which disables the cache..., clear this bit */
+ movl CPU_DM_CONFIG0,%ecx
+ rdmsr
+ andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
+ wrmsr
+
+ /* get cache timing params from BIOS config data locations and apply */
+ /* fix delay controls for DM and IM arrays */
+ /* fix delay controls for DM and IM arrays */
+ movl $CPU_BC_MSS_ARRAY_CTL0, %ecx
+ xorl %edx, %edx
+ movl $0x2814D352, %eax
+ wrmsr
+
+ movl $CPU_BC_MSS_ARRAY_CTL1, %ecx
+ xorl %edx, %edx
+ movl $0x1068334D, %eax
+ wrmsr
+
+ movl $CPU_BC_MSS_ARRAY_CTL2, %ecx
+ movl $0x00000106, %edx
+ movl $0x83104104, %eax
+ wrmsr
+
+ movl $GLCP_FIFOCTL, %ecx
+ rdmsr
+ movl $0x00000005, %edx
+ wrmsr
+
+ /* Enable setting */
+ movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
+ xorl %edx, %edx
+ movl $0x01, %eax
+ wrmsr
+
+ /* Get cleaned up. */
+ xorl %edi, %edi
+ xorl %esi, %esi
+ xorl %ebp, %ebp
+
+ /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + DCACHE_RAM_SIZE for holding stack */
+ /* remember, there is NO stack yet... */
+
+ /* Tell cache we want to fill WAY 0 starting at the top */
+ xorl %edx, %edx
+ xorl %eax, %eax
+ movl $CPU_DC_INDEX, %ecx
+ wrmsr
+
+ /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
+ movl $LX_STACK_BASE, %ebp /* init to start address */
+ orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
+
+ /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
+ movl $LX_NUM_CACHELINES, %edi
+DCacheSetupFillWay:
+
+ /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
+ /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
+ movw $0x04, %si
+ xorl %edx, %edx
+ xorl %eax, %eax
+ movl $CPU_DC_DATA, %ecx
+DCacheSetup_quadWordLoop:
+ wrmsr
+ decw %si
+ jnz DCacheSetup_quadWordLoop
+
+ /* Set the tag for this line, need to do this for every new cache line to validate it! */
+ /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
+ xorl %edx, %edx
+ movl %ebp, %eax
+ movl $CPU_DC_TAG, %ecx
+ wrmsr
+
+ /* switch to next line */
+ /* lines are in Bits10:4 */
+ /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
+ movl $CPU_DC_INDEX, %ecx
+ rdmsr
+ addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
+ wrmsr
+
+ decl %edi
+ jnz DCacheSetupFillWay
+
+ /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
+ addl $LX_CACHEWAY_SIZE, %ebp
+ cmpl $LX_STACK_END, %ebp
+ jge leave_DCacheSetup
+ movl $LX_NUM_CACHELINES, %edi
+
+ /* switch to next way */
+ movl $CPU_DC_INDEX, %ecx
+ rdmsr
+ addl $0x01, %eax
+ andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
+ wrmsr
+
+ jmp DCacheSetupFillWay
+
+leave_DCacheSetup:
+ xorl %edi, %edi
+ xorl %esi, %esi
+ xorl %ebp, %ebp
+
+ /* Disable the cache, but ... DO NOT INVALIDATE the tags. */
+ /* Memory reads and writes will all hit in the cache. */
+ /* Cache updates and memory write-backs will not occur ! */
+ movl %cr0, %eax
+ orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
+ movl %eax, %cr0
+
+ /* Now point sp to the cached stack. */
+ /* The stack will be fully functional at this location. No system memory is required at all ! */
+ /* set up the stack pointer */
+ movl $LX_STACK_END, %eax
+ movl %eax, %esp
+
+ /* test the stack*/
+ movl $0x0F0F05A5A, %edx
+ pushl %edx
+ popl %ecx
+ cmpl %ecx, %edx
+ je DCacheSetupGood
+ movb $0xC5, %al
+ outb %al, $0x80
+DCacheSetupBad:
+ hlt /* issues */
+ jmp DCacheSetupBad
+DCacheSetupGood:
+
+ /* Go do early init and memory setup */
+ call cache_as_ram_main
+
+ /* If you wanted to maintain the stack in memory you would need to set the tags as dirty
+ so the wbinvd would push out the old stack contents to memory */
+ /* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
+ wbinvd
+
+/* the following code is from crt0.S.lb */
+/* This takes the place of the post-CAR funtions that the K8 uses to setup the stack and copy LB low.*/
+
+#ifndef CONSOLE_DEBUG_TX_STRING
+ /* uses: esp, ebx, ax, dx */
+# define __CRT_CONSOLE_TX_STRING(string) \
+ mov string, %ebx ; \
+ CALLSP(crt_console_tx_string)
+
+# if defined(TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
+# else
+# define CONSOLE_DEBUG_TX_STRING(string)
+# endif
+#endif
+
+ /* clear boot_complete flag */
+ xorl %ebp, %ebp
+__main:
+ CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
+
+ /*
+ * Copy data into RAM and clear the BSS. Since these segments
+ * isn\'t really that big we just copy/clear using bytes, not
+ * double words.
+ */
+ intel_chip_post_macro(0x11) /* post 11 */
+
+ cld /* clear direction flag */
+
+ /* copy linuxBIOS from it's initial load location to
+ * the location it is compiled to run at.
+ * Normally this is copying from FLASH ROM to RAM.
+ */
+#if !CONFIG_COMPRESS
+ movl $_liseg, %esi
+ movl $_iseg, %edi
+ movl $_eiseg, %ecx
+ subl %edi, %ecx
+ rep movsb
+#else
+ leal 4+_liseg, %esi
+ leal _iseg, %edi
+ movl %ebp, %esp /* preserve %ebp */
+ movl $-1, %ebp /* last_m_off = -1 */
+ jmp dcl1_n2b
+
+/* ------------- DECOMPRESSION -------------
+
+ Input:
+ %esi - source
+ %edi - dest
+ %ebp - -1
+ cld
+
+ Output:
+ %eax - 0
+ %ecx - 0
+*/
+
+.macro getbit bits
+.if \bits == 1
+ addl %ebx, %ebx
+ jnz 1f
+.endif
+ movl (%esi), %ebx
+ subl $-4, %esi /* sets carry flag */
+ adcl %ebx, %ebx
+1:
+.endm
+
+decompr_literals_n2b:
+ movsb
+
+decompr_loop_n2b:
+ addl %ebx, %ebx
+ jnz dcl2_n2b
+dcl1_n2b:
+ getbit 32
+dcl2_n2b:
+ jc decompr_literals_n2b
+ xorl %eax, %eax
+ incl %eax /* m_off = 1 */
+loop1_n2b:
+ getbit 1
+ adcl %eax, %eax /* m_off = m_off*2 + getbit() */
+ getbit 1
+ jnc loop1_n2b /* while(!getbit()) */
+ xorl %ecx, %ecx
+ subl $3, %eax
+ jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */
+ shll $8, %eax
+ movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */
+ incl %esi
+ xorl $-1, %eax
+ jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */
+ movl %eax, %ebp /* last_m_off = m_off ?*/
+decompr_ebpeax_n2b:
+ getbit 1
+ adcl %ecx, %ecx /* m_len = getbit() */
+ getbit 1
+ adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */
+ jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */
+ incl %ecx /* m_len++ */
+loop2_n2b:
+ getbit 1
+ adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */
+ getbit 1
+ jnc loop2_n2b /* while(!getbit()) */
+ incl %ecx
+ incl %ecx /* m_len += 2 */
+decompr_got_mlen_n2b:
+ cmpl $-0xd00, %ebp
+ adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */
+ movl %esi, %edx
+ leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */
+ rep
+ movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */
+ movl %edx, %esi
+ jmp decompr_loop_n2b
+decompr_end_n2b:
+ intel_chip_post_macro(0x12) /* post 12 */
+
+ movl %esp, %ebp
+#endif
+
+ CONSOLE_DEBUG_TX_STRING($str_pre_main)
+ leal _iseg, %edi
+ jmp *%edi
+
+.Lhlt:
+ intel_chip_post_macro(0xee) /* post fail ee */
+ hlt
+ jmp .Lhlt
+
+#ifdef __CRT_CONSOLE_TX_STRING
+ /* Uses esp, ebx, ax, dx */
+crt_console_tx_string:
+ mov (%ebx), %al
+ inc %ebx
+ cmp $0, %al
+ jne 9f
+ RETSP
+9:
+/* Base Address */
+#ifndef TTYS0_BASE
+#define TTYS0_BASE 0x3f8
+#endif
+/* Data */
+#define TTYS0_RBR (TTYS0_BASE+0x00)
+
+/* Control */
+#define TTYS0_TBR TTYS0_RBR
+#define TTYS0_IER (TTYS0_BASE+0x01)
+#define TTYS0_IIR (TTYS0_BASE+0x02)
+#define TTYS0_FCR TTYS0_IIR
+#define TTYS0_LCR (TTYS0_BASE+0x03)
+#define TTYS0_MCR (TTYS0_BASE+0x04)
+#define TTYS0_DLL TTYS0_RBR
+#define TTYS0_DLM TTYS0_IER
+
+/* Status */
+#define TTYS0_LSR (TTYS0_BASE+0x05)
+#define TTYS0_MSR (TTYS0_BASE+0x06)
+#define TTYS0_SCR (TTYS0_BASE+0x07)
+
+ mov %al, %ah
+10: mov $TTYS0_LSR, %dx
+ inb %dx, %al
+ test $0x20, %al
+ je 10b
+ mov $TTYS0_TBR, %dx
+ mov %ah, %al
+ outb %al, %dx
+
+ jmp crt_console_tx_string
+#endif /* __CRT_CONSOLE_TX_STRING */
+
+#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
+.section ".rom.data"
+str_copying_to_ram: .string "Copying LinuxBIOS to ram.\r\n"
+str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
+.previous
+
+#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
index af5a3f03bc..ce81929b18 100644
--- a/src/cpu/amd/model_lx/cpubug.c
+++ b/src/cpu/amd/model_lx/cpubug.c
@@ -24,34 +24,12 @@
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
-#include <cpu/amd/lxdef.h>
#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-
-
-#if 0
-void
-bug645(void){
- msr_t msr;
- rdmsr(CPU_ID_CONFIG);
- msr.whatever |= ID_CONFIG_SERIAL_SET;
- wrmsr(msr);
-}
-
-void
-bug573(void){
- msr_t msr;
+#include <cpu/amd/lxdef.h>
- msr = rdmsr(MC_GLD_MSR_PM);
- msr.eax &= 0xfff3;
- wrmsr(MC_GLD_MSR_PM);
-}
-#endif
/**************************************************************************
*
@@ -61,14 +39,8 @@ bug573(void){
* PCI cache deadlock
* There is also fix code in cache and PCI functions. This bug is very is pervasive.
*
- * Entry:
- * Exit:
- * Modified:
- *
**************************************************************************/
-static void
-pcideadlock(void)
-{
+static void pcideadlock(void){
msr_t msr;
/*
@@ -77,18 +49,9 @@ pcideadlock(void)
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
- msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
- msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr);
- /* interlock instruction fetches to WS regions with data accesses.
- * This prevents an instruction fetch from going out to PCI if the
- * data side is about to make a request.
- */
- msr = rdmsr(CPU_IM_CONFIG);
- msr.lo |= IM_CONFIG_LOWER_QWT_SET;
- wrmsr(CPU_IM_CONFIG, msr);
/* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
@@ -100,249 +63,6 @@ pcideadlock(void)
wrmsr( CPU_RCONF_E0_FF, msr);
}
-/****************************************************************************
- *
- * CPUbug784
- *
- * Bugtool #784 + #792
- *
- * Fix CPUID instructions for < 3.0 CPUs
- *
- * Entry:
- * Exit:
- * Modified:
- *
- ****************************************************************************/
-
-void bug784(void)
-{
- msr_t msr;
- //static char *name = "Geode by NSC";
-
- /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
- * would do this -- the OS can figure this type of stuff out!
- */
- msr = rdmsr(0x3006);
- msr.hi = 0x646f6547;
- wrmsr(0x3006, msr);
-
- msr = rdmsr(0x3007);
- msr.hi = 0x79622065;
- msr.lo = 0x43534e20;
- wrmsr(0x3007, msr);
-
- msr = rdmsr(0x3002);
- wrmsr(0x3008, msr);
-
- /* More CPUID to match AMD better. #792*/
- msr = rdmsr(0x3009);
- msr.hi = 0x0C0C0A13D;
- msr.lo = 0x00000000;
- wrmsr(0x3009, msr);
-}
-
-/* cpubug 1398: enable MC if we KNOW we have DDR*/
-/**************************************************************************
- *
- * CPUbugIAENG1398
- *
- * ClearQuest #IAENG1398
- * The MC can not be enabled with SDR memory but can for DDR. Enable for
- * DDR here if the setup token is "Default"
- * Add this back to core by default once 2.0 CPUs are not supported.
- * Entry:
- * Exit:
- * Modified:
- *
- **************************************************************************/
-void eng1398(void)
-{
- msr_t msr;
-
- msr = rdmsr(MSR_GLCP+0x17);
- if ((msr.lo & 0xff) <= CPU_REV_2_0) {
- msr = rdmsr(GLCP_SYS_RSTPLL);
- if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
- return;
- }
-
- /* no CMOS/NVRAM to check, so enable MC Clock Gating */
- msr = rdmsr(MC_GLD_MSR_PM);
- msr.lo |= 3; /* enable MC clock gating.*/
- wrmsr(MC_GLD_MSR_PM, msr);
-}
-
-/***************************************************************************
- *
- * CPUbugIAENG2900
- *
- * Clear Quest IAENG00002900, VSS 118.150
- *
- * BTB issue causes blue screen in windows, but the fix is required
- * for all operating systems.
- *
- * Entry:
- * Exit:
- * Modified:
- *
- **************************************************************************/
-void
-eng2900(void)
-{
- msr_t msr;
-
- printk_debug("CPU_BUG:%s\n", __FUNCTION__);
- /* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
- msr = rdmsr(0x3003);
- msr.hi &= 0xFFFFF7FF;
- wrmsr(0x3003, msr);
-
- /* change this value to zero if you need to disable this BTB SWAPSiF. */
- if (1) {
-
- /* Disable enable_actions in DIAGCTL while setting up GLCP */
- msr.hi = 0;
- msr.lo = 0;
- wrmsr(MSR_GLCP + 0x005f, msr);
-
- /* Changing DBGCLKCTL register to GeodeLink */
- msr.hi = 0;
- msr.lo = 0;
- wrmsr(MSR_GLCP + 0x0016, msr);
-
- msr.hi = 0;
- msr.lo = 2;
- wrmsr(MSR_GLCP + 0x0016, msr);
-
- /* The code below sets up the CPU to stall for 4 GeodeLink
- * clocks when CPU is snooped. Because setting XSTATE to 0
- * overrides any other XSTATE action, the code will always
- * stall for 4 GeodeLink clocks after a snoop request goes
- * away even if it occured a clock or two later than a
- * different snoop; the stall signal will never 'glitch high'
- * for only one or two CPU clocks with this code.
- */
-
- /* Send mb0 port 3 requests to upper GeodeLink diag bits
- [63:32] */
- msr.hi = 0;
- msr.lo = 0x80338041;
- wrmsr(MSR_GLIU0 + 0x2005, msr);
-
- /* set5m watches request ready from mb0 to CPU (snoop) */
- msr.hi = 0x5ad68000;
- msr.lo = 0;
- wrmsr(MSR_GLCP + 0x0045, msr);
-
- /* SET4M will be high when state is idle (XSTATE=11) */
- msr.hi = 0;
- msr.lo = 0x0140;
- wrmsr(MSR_GLCP + 0x0044, msr);
-
- /* SET5n to watch for processor stalled state */
- msr.hi = 0x2000;
- msr.lo = 0;
- wrmsr(MSR_GLCP + 0x004D, msr);
-
- /* Writing action number 13: XSTATE=0 to occur when CPU is
- snooped unless we're stalled */
- msr.hi = 0;
- msr.lo = 0x00400000;
- wrmsr(MSR_GLCP + 0x0075, msr);
-
- /* Writing action number 11: inc XSTATE every GeodeLink clock
- unless we're idle */
- msr.hi = 0;
- msr.lo = 0x30000;
- wrmsr(MSR_GLCP + 0x0073, msr);
-
- /* Writing action number 5: STALL_CPU_PIPE when exitting idle
- state or not in idle state */
- msr.hi = 0;
- msr.lo = 0x00430000;
- wrmsr(MSR_GLCP + 0x006D, msr);
-
- /* Writing DIAGCTL Register to enable the stall action and to
- let set5m watch the upper GeodeLink diag bits. */
- msr.hi = 0;
- msr.lo = 0x80004000;
- wrmsr(MSR_GLCP + 0x005f, msr);
- }
-}
-
-void bug118253(void)
-{
- /* GLPCI PIO Post Control shouldn't be enabled */
- msr_t msr;
-
- msr = rdmsr(GLPCI_SPARE);
- msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
- wrmsr(GLPCI_SPARE, msr);
-}
-
-void bug118339(void)
-{
- /* per AMD, do this always */
- msr_t msr = {0,0};
- int msrnum;
-
- /* Disable enable_actions in DIAGCTL while setting up GLCP */
- wrmsr(MSR_GLCP + 0x005f, msr);
-
- /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
- msrnum = MSR_GLCP + 0x042;
- /* msr.hi = 2d6b8000h */;
- msr.hi = 0x596b8000;
- msr.lo = 0x00000a00;
- wrmsr(msrnum, msr);
-
- /* SET3M fires if MBUS changed and VG pri is odd */
- msrnum = MSR_GLCP + 0x043;
- msr.hi = 0x596b8040;
- msr.lo = 0;
- wrmsr(msrnum, msr);
-
- /* Put VG request data on lower diag bus */
- msrnum = MSR_GLIU0 + 0x2005;
- msr.hi = 0;
- msr.lo = 0x80338041;
- wrmsr(msrnum, msr);
-
- /* Increment Y state if SET3M if true */
- msrnum = MSR_GLCP + 0x074;
- msr.hi = 0;
- msr.lo = 0x0000c000;
- wrmsr(msrnum, msr);
-
- /* Set up MBUS action to PRI=3 read of MBIU */
- msrnum = MSR_GLCP + 0x020;
- msr.hi = 0x0000d863;
- msr.lo = 0x20002000;
- wrmsr(msrnum, msr);
-
- /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
- msrnum = MSR_GLCP + 0x071;
- msr.hi = 0;
- msr.lo = 0x00000c00;
- wrmsr(msrnum, msr);
-
- /* Writing DIAGCTL */
- msrnum = MSR_GLCP + 0x005f;
- msr.hi = 0;
- msr.lo = 0x80004000;
- wrmsr(msrnum, msr);
-
- /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
- /* As per Todd Roberts in PBz1094 and PBz1095 */
- /* Moved from CPUREG to CPUBUG per Tom Sylla */
- msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
- msr = rdmsr(msrnum);
- msr.hi |= 8; /* Bit 35 = MCP_IN */
- wrmsr(msrnum, msr);
-}
-
-
-
/****************************************************************************/
/***/
/** DisableMemoryReorder*/
@@ -353,62 +73,18 @@ void bug118339(void)
/** This is safe to do here and not in MC init since there is nothing*/
/** to maintain coherency with and the cache is not enabled yet.*/
/***/
-/***/
-/** Entry:*/
-/** Exit:*/
-/** Modified:*/
-/***/
/****************************************************************************/
-void disablememoryreadorder(void)
-{
+static void disablememoryreadorder(void){
msr_t msr;
- msr = rdmsr(MC_CF8F_DATA);
+ msr = rdmsr(MC_CF8F_DATA);
msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr);
}
-void
-cpubug(void)
-{
-#if 0 //GX3: any CPU bugs to fix here? :)
- msr_t msr;
- int rev;
-
- msr = rdmsr(GLCP_CHIP_REVID);
-
- rev = msr.lo & 0xff;
- if (rev < 0x20) {
- printk_err("%s: rev < 0x20! bailing!\n");
- return;
- }
- printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
- switch(rev)
- {
- case 0x20:
+/* For cpu version C3. Should be the only released version */
+void cpubug(void) {
pcideadlock();
- eng1398();
- /* cs 5530 bug; ignore
- bug752();
- */
- break;
- case 0x21:
- pcideadlock();
- eng1398();
- eng2900();
- bug118339();
- break;
- case 0x22:
- case 0x30:
- break;
- default:
- printk_err("unknown rev %x, bailing\n", rev);
- return;
- }
- bug784();
- bug118253();
disablememoryreadorder();
printk_debug("Done cpubug fixes \n");
-#endif
-
}
diff --git a/src/cpu/amd/model_lx/cpureginit.c b/src/cpu/amd/model_lx/cpureginit.c
index e8ccb13bbb..4607e3dea4 100644
--- a/src/cpu/amd/model_lx/cpureginit.c
+++ b/src/cpu/amd/model_lx/cpureginit.c
@@ -20,77 +20,219 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* ***************************************************************************/
-/* **/
-/* * BIST */
-/* **/
-/* * GX2 BISTs need to be run before BTB or caches are enabled.*/
-/* * BIST result left in registers on failure to be checked with FS2.*/
-/* **/
-/* ***************************************************************************/
-static void
-BIST(void){
- int msrnum;
+/**************************************************************************
+;*
+;* SetDelayControl
+;*
+;*************************************************************************/
+void SetDelayControl(void){
+ unsigned int msrnum, glspeed;
+ unsigned char spdbyte0, spdbyte1;
msr_t msr;
- /* DM*/
- msrnum = CPU_DM_CONFIG0;
- msr = rdmsr(msrnum);
- msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
+ glspeed = GeodeLinkSpeed();
+
+ /* fix delay controls for DM and IM arrays */
+ msrnum = CPU_BC_MSS_ARRAY_CTL0;
+ msr.hi = 0;
+ msr.lo = 0x2814D352;
wrmsr(msrnum, msr);
- msr.lo = 0x00000003F;
- msr.hi = 0x000000000;
- msrnum = CPU_DM_BIST;
+ msrnum = CPU_BC_MSS_ARRAY_CTL1;
+ msr.hi = 0;
+ msr.lo = 0x1068334D;
wrmsr(msrnum, msr);
- outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
- msr.lo &= 0x0F3FF0000;
- if (msr.lo != 0xfeff0000)
- goto BISTFail;
+ msrnum = CPU_BC_MSS_ARRAY_CTL2;
+ msr.hi = 0x00000106;
+ msr.lo = 0x83104104;
+ wrmsr(msrnum,msr);
- msrnum = CPU_DM_CONFIG0;
+ msrnum = GLCP_FIFOCTL;
msr = rdmsr(msrnum);
- msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
+ msr.hi = 0x00000005;
wrmsr(msrnum, msr);
- /* FPU*/
- msr.lo = 0x000000131;
+ /* Enable setting */
+ msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
msr.hi = 0;
- msrnum = CPU_FP_UROM_BIST;
+ msr.lo = 0x00000001;
wrmsr(msrnum, msr);
- outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
- inb(0x80); /* IO delay*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
- while ((msr.lo&0x884) != 0x884)
- msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
- if ((msr.lo&0x642) != 0x642)
- goto BISTFail;
- msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
- msrnum = CPU_FP_UROM_BIST;
- wrmsr(msrnum, msr);
+ /* Debug Delay Control Setup Check
+ Leave it alone if it has been setup. FS2 or something is here.*/
+ msrnum = GLCP_DELAY_CONTROLS;
+ msr = rdmsr(msrnum);
+ if (msr.lo & ~(0x7C0)){
+ return;
+ }
- /* BTB*/
- msr.lo = 0x000000303;
- msr.hi = 0x000000000;
- msrnum = CPU_PF_BTBRMA_BIST;
- wrmsr(msrnum, msr);
+ /*
+ ; Delay Controls based on DIMM loading. UGH!
+ ; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
+ ; Note - We only support module width of 64.
+ */
+ spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
+ if (spdbyte0 !=0xFF){
+ spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
+ }
+ else{
+ spdbyte0=0;
+ }
+
+ spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
+ if (spdbyte1 !=0xFF){
+ spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
+ }
+ else{
+ spdbyte1=0;
+ }
- outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
- msr = rdmsr(msrnum); /* read back for pass fail*/
- if ((msr.lo & 0x3030) != 0x3030)
- goto BISTFail;
- return;
-BISTFail:
- print_err("BIST failed!\n");
- while(1);
+/* The current thinking. Subject to change...
+
+; "FUTURE ROBUSTNESS" PROPOSAL
+; ----------------------------
+; DIMM Max MBUS MC 0x2000001A bits 26:24
+;DIMMs devices Frequency MCP 0x4C00000F Setting vvv
+;----- ------- --------- ---------------------- ----------
+;1 4 400MHz 0x82*100FF 0x56960004 4
+;1 8 400MHz 0x82*100AA 0x56960004 4
+;1 16 400MHz 0x82*10055 0x56960004 4
+;
+;2 4,4 400MHz 0x82710000 0x56960004 4
+;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
+;
+;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
+;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
+;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE ***
+;
+;1 4 <=333MHz 0x83*100FF 0x56960004 3
+;1 8 <=333MHz 0x83*100AA 0x56960004 3
+;1 16 <=333MHz 0x83*100AA 0x56960004 3
+;
+;2 4,4 <=333MHz 0x837100A5 0x56960004 3
+;2 8,8 <=333MHz 0x937100A5 0x56960004 3
+;
+;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
+;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
+;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE ***
+;=========================================================================
+;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
+; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
+; Bits 54:52 should always be set to '111'.
+
+;No VTT termination
+;-------------------------------------
+;ADDR/CTL have 22 ohm series R
+;DQ/DQM/DQS have 33 ohm series R
+;
+; DIMM Max MBUS
+;DIMMs devices Frequency MCP 0x4C00000F Setting
+;----- ------- --------- ----------------------
+;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa.
+;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change,
+;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side.
+;1 8 <=333MHz 0xF2F100FF 0x56960004 3
+;1 16 <=333MHz 0xF2F100FF 0x56960004 3
+*/
+ msr.hi = msr.lo = 0;
+
+ if (spdbyte0 == 0 || spdbyte1 == 0){
+ /* one dimm solution */
+ if (spdbyte1 == 0){
+ msr.hi |= 0x000800000;
+ }
+ spdbyte0 += spdbyte1;
+ if (spdbyte0 > 8){
+ /* large dimm */
+ if (glspeed < 334){
+ msr.hi |= 0x0837100AA;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x082710055;
+ msr.lo |= 0x056960004;
+ }
+ }
+ else if (spdbyte0 > 4){
+ /* medium dimm */
+ if (glspeed < 334){
+ msr.hi |= 0x0837100AA;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x0827100AA;
+ msr.lo |= 0x056960004;
+ }
+ }
+ else{
+ /* small dimm */
+ if (glspeed < 334){
+ msr.hi |= 0x0837100FF;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x0827100FF;
+ msr.lo |= 0x056960004;
+ }
+ }
+ }
+ else{
+ /* two dimm solution */
+ spdbyte0 += spdbyte1;
+ if (spdbyte0 > 24){
+ /* huge dimms */
+ if (glspeed < 334){
+ msr.hi |= 0x0B37100A5;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x0B2710000;
+ msr.lo |= 0x056960004;
+ }
+ }
+ else if (spdbyte0 > 16){
+ /* large dimms */
+ if (glspeed < 334){
+ msr.hi |= 0x0B37100A5;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x0B27100A5;
+ msr.lo |= 0x056960004;
+ }
+ }
+ else if (spdbyte0 >= 8){
+ /* medium dimms */
+ if (glspeed < 334){
+ msr.hi |= 0x0937100A5;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x0C27100A5;
+ msr.lo |= 0x056960004;
+ }
+ }
+ else{
+ /* small dimms */
+ if (glspeed < 334){
+ msr.hi |= 0x0837100A5;
+ msr.lo |= 0x056960004;
+ }
+ else{
+ msr.hi |= 0x082710000;
+ msr.lo |= 0x056960004;
+ }
+ }
+ }
+ wrmsr(GLCP_DELAY_CONTROLS,msr);
+ return;
}
+
/* ***************************************************************************/
/* * cpuRegInit*/
/* ***************************************************************************/
@@ -99,173 +241,78 @@ cpuRegInit (void){
int msrnum;
msr_t msr;
- //GX3 suspend: what is desired?
-
- /* Enable Suspend on Halt*/
- /*msrnum = CPU_XC_CONFIG;
+ /* Castle 2.0 BTM periodic sync period. */
+ /* [40:37] 1 sync record per 256 bytes */
+ msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum);
- msr.lo |= XC_CONFIG_SUSP_ON_HLT;
- wrmsr(msrnum, msr);*/
-
- /* ENable SUSP and allow TSC to run in Suspend */
- /* to keep speed detection happy*/
- /*msrnum = CPU_BC_CONF_0;
- msr = rdmsr(msrnum);
- msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
- wrmsr(msrnum, msr);*/
-
- /* Setup throttling to proper mode if it is ever enabled.*/
- msrnum = 0x04C00001E;
- msr.hi = 0x000000000;
- msr.lo = 0x00000603C;
- wrmsr(msrnum, msr); // GX3 OK +/-
-
+ msr.hi |= (0x8 << 5);
+ wrmsr(msrnum, msr);
-/* Only do this if we are building for 5535*/
-/* */
-/* FooGlue Setup*/
-/* */
-#if 0
- /* Enable CIS mode B in FooGlue*/
- msrnum = MSR_FG + 0x10;
+ /*
+ ; Castle performance setting.
+ ; Enable Quack for fewer re-RAS on the MC
+ */
+ msrnum = GLIU0_ARB;
msr = rdmsr(msrnum);
- msr.lo &= ~3;
- msr.lo |= 2; /* ModeB*/
+ msr.hi &= ~ARB_UPPER_DACK_EN_SET;
+ msr.hi |= ARB_UPPER_QUACK_EN_SET;
wrmsr(msrnum, msr);
-#endif
-
-/* */
-/* Disable DOT PLL. Graphics init will enable it if needed.*/
-/* */
-
-// GX3: Disable DOT PLL? No. Lets tick.
-/* msrnum = GLCP_DOTPLL;
+ msrnum = GLIU1_ARB;
msr = rdmsr(msrnum);
- msr.lo |= DOTPPL_LOWER_PD_SET;
- wrmsr(msrnum, msr); */
+ msr.hi &= ~ARB_UPPER_DACK_EN_SET;
+ msr.hi |= ARB_UPPER_QUACK_EN_SET;
+ wrmsr(msrnum, msr);
-/* */
-/* Enable RSDC*/
-/* */
- msrnum = 0x1301 ;
+ /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
+ msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum);
- msr.lo |= 0x08;
- wrmsr(msrnum, msr); //GX3 OK
-
-
-/* */
-/* BIST*/
-/* */
- /*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
- {
-// BIST();
- }
-
-
-/* */
-/* Enable BTB*/
-/* */
- /* I hate to put this check here but it doesn't really work in cpubug.asm*/
+ msr.lo &= ~0x880;
+ wrmsr(msrnum, msr);
-//GX3: BTB is enabled by default
+ /* Set the Delay Control in GLCP */
+ SetDelayControl();
-/* msrnum = MSR_GLCP+0x17;
+/* Enable RSDC*/
+ msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
- if (msr.lo >= CPU_REV_2_1){
- msrnum = CPU_PF_BTB_CONF;
- msr = rdmsr(msrnum);
- msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
+ msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr);
- }
-
- */
-/* */
-/* FPU impercise exceptions bit*/
-/* */
- /*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
-
-
-// GX3: FPU impercise exceptions bit - what's that?
-/* {
+ /* FPU imprecise exceptions bit */
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
wrmsr(msrnum, msr);
- }
-
- */
-#if 0
- /* */
- /* Cache Overides*/
- /* */
- /* This code disables the data cache. Don't execute this
- * unless you're testing something.
- */
- /* Allow NVRam to override DM Setup*/
- /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
- {
- msrnum = CPU_DM_CONFIG0;
+ /* Power Savers (Do after BIST) */
+ /* Enable Suspend on HLT & PAUSE instructions*/
+ msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
- msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
+ msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr);
- }
- /* This code disables the instruction cache. Don't execute
- * this unless you're testing something.
- */
- /* Allow NVRam to override IM Setup*/
- /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
- {
- msrnum = CPU_IM_CONFIG;
+
+ /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
+ msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
- msr.lo |= IM_CONFIG_LOWER_ICD_SET;
+ msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
+ msr.lo &= 0x0F0FFFFFF;
+ msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
wrmsr(msrnum, msr);
- }
-#endif
-}
-
-
-
-/* ***************************************************************************/
-/* **/
-/* * MTestPinCheckBX*/
-/* **/
-/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
-/* * This version is called when there isn't a stack available*/
-/* **/
-/* ***************************************************************************/
-static void
-MTestPinCheckBX (void){
- int msrnum;
- msr_t msr;
-
- /*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
- /* return ; */
- /* } */
-
- /* Turn on MTEST*/
- msrnum = MC_CFCLK_DBUG;
- msr = rdmsr(msrnum);
- msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
+ /* Disable the debug clock to save power.*/
+ /* NOTE: leave it enabled for fs2 debug */
+/* msrnum = GLCP_DBGCLKCTL;
+ msr.hi = 0;
+ msr.lo = 0;
wrmsr(msrnum, msr);
+*/
- msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/;
- msr = rdmsr(msrnum);
- msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT;
- if (msr.lo & 1) {
- msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/
- msr = rdmsr(msrnum);
- msr.lo |= CFCLK_LOWER_SDCLK_SET;
- msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET;
+ /* Setup throttling delays to proper mode if it is ever enabled. */
+ msrnum = GLCP_TH_OD;
+ msr.hi = 0;
+ msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
}
-
- /* Lock the cache down here.*/
- __asm__("wbinvd\n");
-
-}
diff --git a/src/cpu/amd/model_lx/model_lx_init.c b/src/cpu/amd/model_lx/model_lx_init.c
index 541b3649ce..1cdfda8e54 100644
--- a/src/cpu/amd/model_lx/model_lx_init.c
+++ b/src/cpu/amd/model_lx/model_lx_init.c
@@ -46,7 +46,6 @@ static void model_lx_init(device_t dev)
printk_debug("model_lx_init\n");
/* Turn on caching if we haven't already */
-
x86_enable_cache();
/* Enable the local cpu apics */
@@ -60,7 +59,7 @@ static void model_lx_init(device_t dev)
outb(0x02,0x92);
printk_debug("A20 (0x92): %d\n",inb(0x92));
- printk_debug("model_lx_init DONE\n");
+ printk_debug("CPU model_lx_init DONE\n");
};
static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c
index d2e4cf11da..4bc362c52c 100644
--- a/src/cpu/amd/model_lx/syspreinit.c
+++ b/src/cpu/amd/model_lx/syspreinit.c
@@ -21,8 +21,6 @@
*/
/* ***************************************************************************/
-
-/* ***************************************************************************/
/* **/
/* * StartTimer1*/
/* **/
@@ -41,6 +39,8 @@ void
SystemPreInit(void){
/* they want a jump ... */
- __asm__("jmp .+2\ninvd\njmp.+2\n");
+#ifndef USE_DCACHE_RAM
+ __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
+#endif
StartTimer1();
}
diff --git a/src/cpu/amd/model_lx/vsmsetup.c b/src/cpu/amd/model_lx/vsmsetup.c
index 0a5f792b49..e2922e1859 100644
--- a/src/cpu/amd/model_lx/vsmsetup.c
+++ b/src/cpu/amd/model_lx/vsmsetup.c
@@ -69,6 +69,9 @@
* software, even if advised of the possibility of such damage.
*
* $Id: vsmsetup.c,v 1.8 2006/09/08 12:47:57 andrei Exp $
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
*--------------------------------------------------------------------*/
/* Modified to be a self sufficient plug in so that it can be used
@@ -300,13 +303,13 @@ void do_vsmbios(void)
printk_err("do_vsmbios\n");
/* clear vsm bios data area */
for (i = 0x400; i < 0x500; i++) {
- *(unsigned char *) i = 0;
+ *(volatile unsigned char *) i = 0;
}
/* declare rom address here - keep any config data out of the way
* of core LXB stuff */
- /* this is the base of rom on the GX2 at present. At some point, this has to be
+ /* this is the base of rom on the LX at present. At some point, this has to be
* much better parameterized
*/
//rom = 0xfff80000;
@@ -314,8 +317,10 @@ void do_vsmbios(void)
/* the VSA starts at the base of rom - 64 */
//rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024);
- rom = 0xfffc8000;
+ //rom = 0xfffc8000;
+ //VSA is cat onto the end after LB builds
+ rom = ((unsigned long) 0) - (ROM_SIZE + 36 * 1024);
buf = (unsigned char *) VSA2_BUFFER;
olen = unrv2b((uint8_t *)rom, buf, &ilen);
printk_debug("buf ilen %d olen%d\n", ilen, olen);
diff --git a/src/include/cpu/amd/geode_post_code.h b/src/include/cpu/amd/geode_post_code.h
new file mode 100644
index 0000000000..5a0e57689a
--- /dev/null
+++ b/src/include/cpu/amd/geode_post_code.h
@@ -0,0 +1,196 @@
+/*
+* This file is part of the LinuxBIOS project.
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License version 2 as
+* published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+/* standard AMD post definitions -- might as well use them. */
+#define POST_Output_Port (0x080) /* port to write post codes to*/
+
+#define POST_preSioInit (0x000) /* geode.asm*/
+#define POST_clockInit (0x001) /* geode.asm*/
+#define POST_CPURegInit (0x002) /* geode.asm*/
+#define POST_UNREAL (0x003) /* geode.asm*/
+#define POST_CPUMemRegInit (0x004) /* geode.asm*/
+#define POST_CPUTest (0x005) /* geode.asm*/
+#define POST_memSetup (0x006) /* geode.asm*/
+#define POST_memSetUpStack (0x007) /* geode.asm*/
+#define POST_memTest (0x008) /* geode.asm*/
+#define POST_shadowRom (0x009) /* geode.asm*/
+#define POST_memRAMoptimize (0x00A) /* geode.asm*/
+#define POST_cacheInit (0x00B) /* geode.asm*/
+#define POST_northBridgeInit (0x00C) /* geode.asm*/
+#define POST_chipsetInit (0x00D) /* geode.asm*/
+#define POST_sioTest (0x00E) /* geode.asm*/
+#define POST_pcATjunk (0x00F) /* geode.asm*/
+
+
+#define POST_intTable (0x010) /* geode.asm*/
+#define POST_memInfo (0x011) /* geode.asm*/
+#define POST_romCopy (0x012) /* geode.asm*/
+#define POST_PLLCheck (0x013) /* geode.asm*/
+#define POST_keyboardInit (0x014) /* geode.asm*/
+#define POST_cpuCacheOff (0x015) /* geode.asm*/
+#define POST_BDAInit (0x016) /* geode.asm*/
+#define POST_pciScan (0x017) /* geode.asm*/
+#define POST_optionRomInit (0x018) /* geode.asm*/
+#define POST_ResetLimits (0x019) /* geode.asm*/
+#define POST_summary_screen (0x01A) /* geode.asm*/
+#define POST_Boot (0x01B) /* geode.asm*/
+#define POST_SystemPreInit (0x01C) /* geode.asm*/
+#define POST_ClearRebootFlag (0x01D) /* geode.asm*/
+#define POST_GLIUInit (0x01E) /* geode.asm*/
+#define POST_BootFailed (0x01F) /* geode.asm*/
+
+
+#define POST_CPU_ID (0x020) /* cpucpuid.asm*/
+#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/
+#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/
+#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/
+#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/
+#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/
+#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/
+#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/
+#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/
+#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/
+#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/
+#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/
+#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/
+#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/
+#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/
+#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/
+
+
+
+/* PCI config*/
+#define P80_PCICFG (0x030) /* pcispace.asm*/
+
+
+/* PCI io*/
+#define P80_PCIIO (0x040) /* pcispace.asm*/
+
+
+/* PCI memory*/
+#define P80_PCIMEM (0x050) /* pcispace.asm*/
+
+
+/* SIO*/
+#define P80_SIO (0x060) /* *sio.asm*/
+
+/* Memory Setp*/
+#define P80_MEM_SETUP (0x070) /* docboot meminit*/
+#define POST_MEM_SETUP (0x070) /* memsize.asm*/
+#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/
+#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/
+#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/
+#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/
+#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/
+#define POST_MEM_ENABLE (0x076) /* memsize.asm*/
+#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/
+#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/
+#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/
+#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/
+#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/
+#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/
+#define ERROR_BANK_SET (0x07d) /* memsize.asm*/
+#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/
+#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/
+
+
+#define POST_UserPreInit (0x080) /* geode.asm*/
+#define POST_UserPostInit (0x081) /* geode.asm*/
+#define POST_Equipment_check (0x082) /* geode.asm*/
+#define POST_InitNVRAMBX (0x083) /* geode.asm*/
+#define POST_NoPIRTable (0x084) /* pci.asm*/
+#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/
+#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/
+#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/
+#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/
+#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/
+#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/
+#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/
+#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/
+#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/
+#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/
+
+
+#define POST_STACK_SETUP (0x090) /* memstack.asm*/
+#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/
+#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/
+#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/
+#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/
+#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/
+#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/
+#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/
+#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/
+
+
+#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/
+#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/
+#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/
+#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/
+#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/
+#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/
+#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/
+
+
+#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/
+#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/
+#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/
+#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/
+#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/
+#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/
+#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/
+
+
+#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/
+#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/
+#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/
+#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
+#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/
+#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/
+#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/
+#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/
+#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/
+#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/
+#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/
+#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/
+#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/
+#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/
+
+#define POST_RCONFInitError (0x0CE) /* cache.asm*/
+#define POST_CacheInitError (0x0CF) /* cache.asm*/
+
+
+#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/
+#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/
+#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/
+#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/
+#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/
+#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/
+#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/
+#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/
+#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/
+#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/
+#define POST_ROM_POSTUNCOMPRESS (0x0DE)
+
+
+#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/
+#define POST_PreChipsetInit (0x0E1) /* geode.asm*/
+#define POST_LateChipsetInit (0x0E2) /* geode.asm*/
+#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/
+
+
+#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index 6d5f412241..fbe7b6edae 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -24,42 +24,21 @@
#ifndef CPU_AMD_LXDEF_H
#define CPU_AMD_LXDEF_H
-#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
-#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
-#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
-#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/
-
-#define CPU_REV_1_0 0x011
-#define CPU_REV_1_1 0x012
-#define CPU_REV_1_2 0x013
-#define CPU_REV_1_3 0x014
+
+#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/
+#define CPU_ID_2_0 0x000005A1
+#define CPU_ID_3_0 0x000005A2
+
+#define CPU_REV_1_0 0x010
+#define CPU_REV_1_1 0x011
#define CPU_REV_2_0 0x020
#define CPU_REV_2_1 0x021
#define CPU_REV_2_2 0x022
-#define CPU_REV_3_0 0x030
-/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
-#define GLCP_CLK_DIS_DELAY 0x4c000008
-#define GLCP_PMCLKDISABLE 0x4c000009
-#define GLCP_CHIP_REVID 0x4c000017
-
-/* GLCP_SYS_RSTPLL, Upper 32 bits */
-#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
-#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
-#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
-
-/* GLCP_SYS_RSTPLL, Lower 32 bits */
-#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
-#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
-
-#define GLCP_SYS_RSTPLL_LOCKWAIT 24
-#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
-#define GLCP_SYS_RSTPLL_BYPASS 15
-#define GLCP_SYS_RSTPLL_PD 14
-#define GLCP_SYS_RSTPLL_RESETPLL 13
-#define GLCP_SYS_RSTPLL_DDRMODE 10
-#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
-#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
-#define GLCP_SYS_RSTPLL_CHIP_RESET 0
+#define CPU_REV_C_0 0x030
+#define CPU_REV_C_1 0x031
+#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/
+#define CPU_REV_C_3 0x033
+
/* MSR routing as follows*/
/* MSB = 1 means not for CPU*/
@@ -67,80 +46,57 @@
/* next3 bits next port if through an GLIU*/
/* etc...*/
-/*Redcloud as follows.*/
-/* GLIU0*/
-/* port0 - GLIU0*/
-/* port1 - MC*/
-/* port2 - GLIU1*/
-/* port3 - CPU*/
-/* port4 - VG*/
-/* port5 - GP*/
-/* port6 - DF*/
-
-/* GLIU1*/
-/* port1 - GLIU0*/
-/* port3 - GLCP*/
-/* port4 - PCI*/
-/* port5 - FG*/
-
-
-/* start GX3 def, differences are marked with GX3 comment */
-
+/* GLIU0 ports */
#define GL0_GLIU0 0
#define GL0_MC 1
#define GL0_GLIU1 2
#define GL0_CPU 3
#define GL0_VG 4
#define GL0_GP 5
-//#define GL0_DF 6 //GX3 no such thing as VP port
+/* GLIU1 ports */
#define GL1_GLIU0 1
-//GX3 VP port
#define GL1_DF 2
#define GL1_GLCP 3
#define GL1_PCI 4
#define GL1_VIP 5
#define GL1_AES 6
-#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
+
+#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
-#define MSR_CPU (GL0_CPU << 32) /* 0000xxxx - this is not used for BIOS */ //GX3
+#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
#define MSR_GP (GL0_GP << 29) /* A000xxxx */
-//#define MSR_DF (GL0_DF << 29) /* C000xxxx */ //GX3 no such thing
-#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
-#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
-//#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ //GX3: no such thing
+#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
+#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
+#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
-/* South Bridge*/
-#define SB_PORT 2 /* port of the SouthBridge */
-#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* 5100xxxx - address to the SouthBridge*/
-#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
+#define MSR_FG MSR_GLCP
-
-/**/
/*GeodeLink Interface Unit 0 (GLIU0) port0*/
-/**/
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
+#define GLIU0_GLD_MSR_ERROR (MSR_GLIU0 + 0x2003)
#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
#define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20)
#define GLIU0_CAP (MSR_GLIU0 + 0x86)
#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
+#define GLIU0_ARB (MSR_GLIU0 + 0x82)
+#define ARB_UPPER_QUACK_EN_SET (1 << 31)
+#define ARB_UPPER_DACK_EN_SET (1 << 28)
-/**/
/* Memory Controller GLIU0 port 1*/
-/**/
+
#define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
#define MC_GLD_MSR_PM (MSR_MC + 0x2004)
#define MC_CF07_DATA (MSR_MC + 0x18)
-
#define CF07_UPPER_D1_SZ_SHIFT 28
#define CF07_UPPER_D1_MB_SHIFT 24
#define CF07_UPPER_D1_CB_SHIFT 20
@@ -160,52 +116,56 @@
#define MC_CF8F_DATA (MSR_MC + 0x19)
-
#define CF8F_UPPER_XOR_BS_SHIFT 19
#define CF8F_UPPER_XOR_MB0_SHIFT 18
#define CF8F_UPPER_XOR_BA1_SHIFT 17
#define CF8F_UPPER_XOR_BA0_SHIFT 16
#define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
-#define CF8F_UPPER_REG_DIMM_SHIFT 4
#define CF8F_LOWER_CAS_LAT_SHIFT 28
-#define CF8F_LOWER_REF2ACT_SHIFT 24
+#define CF8F_LOWER_ACT2ACTREF_SHIFT 24
#define CF8F_LOWER_ACT2PRE_SHIFT 20
#define CF8F_LOWER_PRE2ACT_SHIFT 16
#define CF8F_LOWER_ACT2CMD_SHIFT 12
#define CF8F_LOWER_ACT2ACT_SHIFT 8
-#define CF8F_UPPER_32BIT_SET (1 << 5)
#define CF8F_UPPER_HOI_LOI_SET (1 << 1)
#define MC_CF1017_DATA (MSR_MC + 0x1A)
-
+#define CF1017_LOWER_WR_TO_RD_SHIFT 28
+#define CF1017_LOWER_RD_TMG_CTL_SHIFT 24
+#define CF1017_LOWER_REF2ACT_SHIFT 16
#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
#define CF1017_LOWER_WR2DAT_SHIFT 0
#define MC_CFCLK_DBUG (MSR_MC + 0x1D)
#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
-#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
+#define CFCLK_UPPER_MTST_RBEX_EN_SET (1 << 1)
#define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
+#define CFCLK_LOWER_FORCE_PRE_SET (1 << 16)
+#define CFCLK_LOWER_TRISTATE_DIS_SET (1 << 12)
#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
#define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
#define MC_CF_RDSYNC (MSR_MC + 0x1F)
+#define MC_CF_PMCTR (MSR_MC + 0x20)
-/**/
/* GLIU1 GLIU0 port2*/
-/**/
+
#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
+#define GLIU1_GLD_MSR_ERROR (MSR_GLIU1 + 0x2003)
#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
+#define GLIU1_PORT_ACTIVE (MSR_GLIU1 + 0x81)
+#define GLIU1_ARB (MSR_GLIU1 + 0x82)
+
-/**/
/* CPU ; does not need routing instructions since we are executing there.*/
-/**/
+
#define CPU_GLD_MSR_CAP 0x2000
#define CPU_GLD_MSR_CONFIG 0x2001
#define CPU_GLD_MSR_PM 0x2004
@@ -216,22 +176,41 @@
#define DIAG_SEL0__MODE_SHIFT 0
#define DIAG_SET0_SET (1 << 15)
-#define CPU_PF_BTB_CONF 0x1100
-#define BTB_ENABLE_SET (1 << 0)
+#define CPU_PF_CONF 0x1100
#define RETURN_STACK_ENABLE_SET (1 << 4)
-#define CPU_PF_BTBRMA_BIST 0x110C
+#define PF_CONF_CC_L1 (1 << 0)
+#define CPU_PF_INVD 0x1102
+#define PF_RS_INVD_SET (1 << 1)
+#define PF_CC_INVD_SET (1 << 0)
+#define CPU_PF_BIST 0x1140
#define CPU_XC_CONFIG 0x1210
#define XC_CONFIG_SUSP_ON_HLT (1 << 0)
+#define XC_CONFIG_SUSP_ON_PAUSE (1 << 1)
+
#define CPU_ID_CONFIG 0x1250
#define ID_CONFIG_SERIAL_SET (1 << 0)
#define CPU_AC_MSR 0x1301
+
+/* SMM*/
+#define CPU_AC_SMM_CTL 0x1301
+#define SMM_NMI_EN_SET (1 << 0)
+#define SMM_SUSP_EN_SET (1 << 1)
+#define NEST_SMI_EN_SET (1 << 2)
+#define SMM_INST_EN_SET (1 << 3)
+#define INTL_SMI_EN_SET (1 << 4)
+#define EXTL_SMI_EN_SET (1 << 5)
+
#define CPU_EX_BIST 0x1428
/*IM*/
#define CPU_IM_CONFIG 0x1700
+#define IM_CONFIG_LOWER_SERIAL_SET (1 << 2)
+#define IM_CONFIG_LOWER_L0WE_SET (1 << 6)
#define IM_CONFIG_LOWER_ICD_SET (1 << 8)
+#define IM_CONFIG_LOWER_EBE_SET (1 << 10)
+#define IM_CONFIG_LOWER_ABSE_SET (1 << 11)
#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
#define CPU_IC_INDEX 0x1710
#define CPU_IC_DATA 0x1711
@@ -245,20 +224,14 @@
#define CPU_IM_BIST_DATA 0x1731
-/* ----- GX3 OK ---- */
-
-/* various CPU MSRs */
+/*DM MSR MAP*/
#define CPU_DM_CONFIG0 0x1800
#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
-#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
+#define DM_CONFIG0_LOWER_EVCTONRPL_SET (1 << 14)
#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
+#define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8)
#define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
-#define CPU_DM_CONFIG1 0x1801
-
-#define CPU_DM_PFLOCK 0x1804
-
-/* configuration MSRs */
#define CPU_RCONF_DEFAULT 0x1808
#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
@@ -267,16 +240,11 @@
#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
-
#define CPU_RCONF_BYPASS 0x180A
#define CPU_RCONF_A0_BF 0x180B
#define CPU_RCONF_C0_DF 0x180C
#define CPU_RCONF_E0_FF 0x180D
-/* ------------------------ */
-
-/* ----- GX3 OK ---- */
-
#define CPU_RCONF_SMM 0x180E
#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
#define RCONF_SMM_UPPER_RCSMM_SHIFT 0
@@ -284,9 +252,6 @@
#define RCONF_SMM_LOWER_RCNORM_SHIFT 0
#define RCONF_SMM_LOWER_EN_SET (1<<8)
-/* ------------------------ */
-
-
#define CPU_RCONF_DMM 0x180F
#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
#define RCONF_DMM_UPPER_RCDMM_SHIFT 0
@@ -294,10 +259,6 @@
#define RCONF_DMM_LOWER_RCNORM_SHIFT 0
#define RCONF_DMM_LOWER_EN_SET (1<<8)
-
-
-/* ----- GX3 OK ---- */
-
#define CPU_RCONF0 0x1810
#define CPU_RCONF1 0x1811
#define CPU_RCONF2 0x1812
@@ -306,20 +267,10 @@
#define CPU_RCONF5 0x1815
#define CPU_RCONF6 0x1816
#define CPU_RCONF7 0x1817
-
-/* ------------------------ */
-
-/* ----- GX3 OK ---- */
-
#define CPU_CR1_MSR 0x1881
#define CPU_CR2_MSR 0x1882
#define CPU_CR3_MSR 0x1883
#define CPU_CR4_MSR 0x1884
-
-/* ------------------------ */
-
-/* ----- GX3 OK ---- */
-
#define CPU_DC_INDEX 0x1890
#define CPU_DC_DATA 0x1891
#define CPU_DC_TAG 0x1892
@@ -329,48 +280,83 @@
#define CPU_DTB_LRU 0x1899
#define CPU_DTB_ENTRY 0x189A
#define CPU_DTB_ENTRY_I 0x189B
-
-/* ------------------------ */
-
#define CPU_L2TB_INDEX 0x189C
#define CPU_L2TB_LRU 0x189D
#define CPU_L2TB_ENTRY 0x189E
#define CPU_L2TB_ENTRY_I 0x189F
#define CPU_DM_BIST 0x18C0
- /* SMM*/
-#define CPU_AC_SMM_CTL 0x1301
-#define SMM_NMI_EN_SET (1<<0)
-#define SMM_SUSP_EN_SET (1<<1)
-#define NEST_SMI_EN_SET (1<<2)
-#define SMM_INST_EN_SET (1<<3)
-#define INTL_SMI_EN_SET (1<<4)
-#define EXTL_SMI_EN_SET (1<<5)
-
-#define CPU_FPU_MSR_MODE 0x1A00
-#define FPU_IE_SET (1<<0)
-
-#define CPU_FP_UROM_BIST 0x1A03
#define CPU_BC_CONF_0 0x1900
#define TSC_SUSP_SET (1<<5)
#define SUSP_EN_SET (1<<12)
-/* L2 cache*/
-
-#define L2_CONFIG_MSR 0x1920
-#define L2_STATUS_MSR 0x1921
-#define L2_BIST_MSR 0x1926
+#define CPU_BC_CONF_1 0x1901
+#define CPU_BC_MSR_LOCK 0x1908
+#define CPU_BC_L2_CONF 0x1920
+#define BC_L2_ENABLE_SET (1 << 0)
+#define BC_L2_ALLOC_ENABLE_SET (1 << 1)
+#define BC_L2_DM_ALLOC_ENABLE_SET (1 << 2)
+#define BC_L2_IM_ALLOC_ENABLE_SET (1 << 3)
+#define BC_L2_INVALIDATE_SET (1 << 4)
+#define CPU_BC_L2_STATUS 0x1921
+#define CPU_BC_L2_INDEX 0x1922
+#define CPU_BC_L2_DATA 0x1923
+#define CPU_BC_L2_TAG 0x1924
+#define CPU_BC_L2_TAG_AUTOINC 0x1925
+#define CPU_BC_L2_BIST 0x1926
+#define BC_L2_BIST_TAG_ENABLE_SET (1 << 0)
+#define BC_L2_BIST_TAG_DRT_EN_SET (1 << 1)
+#define BC_L2_BIST_DATA_ENABLE_SET (1 << 2)
+#define BC_L2_BIST_DATA_DRT_EN_SET (1 << 3)
+#define BC_L2_BIST_MRU_ENABLE_SET (1 << 4)
+#define BC_L2_BIST_MRU_DRT_EN_SET (1 << 5)
+#define CPU_BC_PMODE_MSR 0x1930
+#define CPU_BC_MSS_ARRAY_CTL_ENA 0x1980
+#define CPU_BC_MSS_ARRAY_CTL0 0x1981
+#define CPU_BC_MSS_ARRAY_CTL1 0x1982
+#define CPU_BC_MSS_ARRAY_CTL2 0x1983
+
+#define CPU_FPU_MSR_MODE 0x1A00
+#define FPU_IE_SET (1 << 0)
+
+#define CPU_FP_UROM_BIST 0x1A03
+
+#define CPU_CPUID0 0x3000
+#define CPU_CPUID1 0x3001
+#define CPU_CPUID2 0x3002
+#define CPU_CPUID3 0x3003
+#define CPU_CPUID4 0x3004
+#define CPU_CPUID5 0x3005
+#define CPU_CPUID6 0x3006
+#define CPU_CPUID7 0x3007
+#define CPU_CPUID8 0x3008
+#define CPU_CPUID9 0x3009
+#define CPU_CPUIDA 0x300A
+#define CPU_CPUIDB 0x300B
+#define CPU_CPUIDC 0x300C
+#define CPU_CPUIDD 0x300D
+#define CPU_CPUIDE 0x300E
+#define CPU_CPUIDF 0x300F
+#define CPU_CPUID10 0x3010
+#define CPU_CPUID11 0x3011
+#define CPU_CPUID12 0x3012
+#define CPU_CPUID13 0x3013
+
-
- /**/
/* VG GLIU0 port4*/
- /**/
+
#define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
#define VG_GLD_MSR_PM (MSR_VG + 0x2004)
+#define VG_BIST (MSR_VG + 0x2010)
+
+
+
+/* GP GLIU0 port5*/
+
#define GP_GLD_MSR_CAP (MSR_GP + 0x2000)
#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
@@ -378,57 +364,64 @@
-/**/
/* DF GLIU0 port6*/
-/**/
-/*
+
+
#define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
#define DF_LOWER_LCD_SHIFT 6
#define DF_GLD_MSR_PM (MSR_DF + 0x2004)
+#define DF_BIST (MSR_DF + 0x2005)
+
-*/
-/**/
/* GeodeLink Control Processor GLIU1 port3*/
-/**/
+
#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
+#define GLCP_GLD_MSR_SMI (MSR_GLCP + 0x2002)
+#define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003)
#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
-
-#define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W*/)
-#define RSTPLL_UPPER_MDIV_SHIFT 9
-#define RSTPLL_UPPER_VDIV_SHIFT 6
-#define RSTPLL_UPPER_FBDIV_SHIFT 0
-
+#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */
+#define RSTPLL_UPPER_GLMULT_SHIFT 7
+#define RSTPLL_UPPER_GLDIV_SHIFT 6
+#define RSTPLL_UPPER_CPUMULT_SHIFT 1
+#define RSTPLL_UPPER_CPUDIV_SHIFT 0
#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
-#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
-
+#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
-#define RSTPPL_LOWER_BYPASS_SHIFT 15
-#define RSTPPL_LOWER_TST_SHIFT 11
-#define RSTPPL_LOWER_SDRMODE_SHIFT 10
-#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
-
-#define RSTPPL_LOWER_LOCK_SET (1<<25)
-#define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
-#define RSTPPL_LOWER_BYPASS_SET (1<<15)
-#define RSTPPL_LOWER_PD_SET (1<<14)
-#define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
-#define RSTPPL_LOWER_SDRMODE_SET (1<<10)
+#define RSTPPL_LOWER_COREBYPASS_SHIFT 12
+#define RSTPPL_LOWER_GLBYPASS_SHIFT 11
+#define RSTPPL_LOWER_PCISPEED_SHIFT 7
+#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1
+#define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
+
+#define RSTPPL_LOWER_GLLOCK_SET (1 << 25)
+#define RSTPPL_LOWER_CORELOCK_SET (1 << 24)
+#define RSTPPL_LOWER_LOCKWAIT_SET (1 << 15)
+#define RSTPPL_LOWER_CLPD_SET (1 << 14)
+#define RSTPPL_LOWER_COREPD_SET (1 << 13)
+#define RSTPPL_LOWER_MBBYPASS_SET (1 << 12)
+#define RSTPPL_LOWER_COREBYPASS_SET (1 << 11)
+#define RSTPPL_LOWER_LPFEN_SET (1 << 10)
#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
-#define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W*/)
-#define DOTPPL_LOWER_PD_SET (1<<14)
+#define GLCP_DOWSER (MSR_GLCP + 0x0E)
+#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16)
+#define GLCP_REVID (MSR_GLCP + 0x17)
+#define GLCP_TH_OD (MSR_GLCP + 0x1E)
+#define GLCP_FIFOCTL (MSR_GLCP + 0x5E)
+#define GLCP_BIST GLCP_FIFOCTL
+
+#define MSR_INIT (MSR_GLCP + 0x33)
-/**/
/* GLIU1 port 4*/
-/**/
+
#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
@@ -437,10 +430,13 @@
#define GLPCI_CTRL_UPPER_FTH_SHIFT 28
#define GLPCI_CTRL_UPPER_RTH_SHIFT 24
#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
+#define GLPCI_CTRL_UPPER_RTL_SHIFT 17
#define GLPCI_CTRL_UPPER_DTL_SHIFT 14
#define GLPCI_CTRL_UPPER_WTO_SHIFT 11
-#define GLPCI_CTRL_UPPER_LAT_SHIFT 3
+#define GLPCI_CTRL_UPPER_SLTO_SHIFT 10
#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
+#define GLPCI_CTRL_UPPER_LAT_SHIFT 3
+
#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
#define GLPCI_CTRL_LOWER_ER_SET (1<<11)
@@ -451,15 +447,19 @@
#define GLPCI_CTRL_LOWER_ME_SET (1<<0)
#define GLPCI_ARB (MSR_PCI + 0x2011)
-#define GLPCI_ARB_UPPER_CR_SHIFT (28)
-#define GLPCI_ARB_UPPER_R2_SHIFT (24)
-#define GLPCI_ARB_UPPER_R1_SHIFT (20)
-#define GLPCI_ARB_UPPER_R0_SHIFT (16)
-#define GLPCI_ARB_UPPER_CH_SHIFT (12)
-#define GLPCI_ARB_UPPER_H2_SHIFT (8)
-#define GLPCI_ARB_UPPER_H1_SHIFT (4)
-#define GLPCI_ARB_UPPER_H0_SHIFT (0)
+#define GLPCI_ARB_UPPER_CR_SHIFT 28
+#define GLPCI_ARB_UPPER_R2_SHIFT 24
+#define GLPCI_ARB_UPPER_R1_SHIFT 20
+#define GLPCI_ARB_UPPER_R0_SHIFT 16
+#define GLPCI_ARB_UPPER_CH_SHIFT 12
+#define GLPCI_ARB_UPPER_H2_SHIFT 8
+#define GLPCI_ARB_UPPER_H1_SHIFT 4
+#define GLPCI_ARB_UPPER_H0_SHIFT 0
+
#define GLPCI_ARB_LOWER_COV_SET (1<<23)
+#define GLPCI_ARB_LOWER_VO2_SET (1 << 22)
+#define GLPCI_ARB_LOWER_OV1_SET (1 << 21)
+#define GLPCI_ARB_LOWER_OV0_SET (1 << 20)
#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
@@ -469,6 +469,8 @@
#define GLPCI_ARB_LOWER_PRE0_SET (1<<8)
#define GLPCI_ARB_LOWER_BM1_SET (1<<7)
#define GLPCI_ARB_LOWER_BM0_SET (1<<6)
+#define GLPCI_ARB_LOWER_EA_SET (1 << 2)
+#define GLPCI_ARB_LOWER_BMD_SET (1 << 1)
#define GLPCI_ARB_LOWER_PARK_SET (1<<0)
#define GLPCI_REN (MSR_PCI + 0x2014)
@@ -487,7 +489,9 @@
#define GLPCI_RC_LOWER_WC_SET (1<<4)
#define GLPCI_RC_LOWER_WP_SET (1<<2)
#define GLPCI_RC_LOWER_CD_SET (1<<0)
-#define GLPCI_EXT_MSR (MSR_PCI + 0x201E)
+
+#define GLPCI_ExtMSR (MSR_PCI + 0x201E)
+
#define GLPCI_SPARE (MSR_PCI + 0x201F)
#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
@@ -498,27 +502,30 @@
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
-/**/
-/* FooGlue GLIU1 port 5*/
-/**/
-/* GX3 not needed?
-#define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
-#define FG_GLD_MSR_PM (MSR_FG + 0x2004)
-*/
+
/* VIP GLIU1 port 5*/
-/* */
+
#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
#define VIP_BIST (MSR_VIP + 0x2005)
-/* */
+
/* AES GLIU1 port 6*/
-/* */
+
#define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
#define AES_CONTROL (MSR_AES + 0x2006)
-/* more fun stuff */
+
+
+/* from MC spec */
+#define MIN_MOD_BANKS 1
+#define MAX_MOD_BANKS 2
+#define MIN_DEV_BANKS 2
+#define MAX_DEV_BANKS 4
+#define MAX_COL_ADDR 17
+
+/* GLIU typedefs */
#define BM 1 /* Base Mask - map power of 2 size aligned region*/
#define BMO 2 /* BM with an offset*/
#define R 3 /* Range - 4k range minimum*/
@@ -539,10 +546,10 @@
#define MSR_GL0 (GL1_GLIU0 << 29)
+
+/* Platform stuff but unlikely to change */
/* Set up desc addresses from 20 - 3f*/
/* This is chip specific!*/
-
-/* ---------- GX3 OK -------------- */
#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
#define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/
@@ -609,656 +616,13 @@
#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
+#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
/* ------------------------ */
-#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
+#define SMM_OFFSET 0x80400000 /* above 2GB */
+#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
+
-/* definitions that are "once you are mostly up, start VSA" type things */
-#define SMM_OFFSET (0x40400000)
-#define SMM_SIZE (256)
-#define DMM_OFFSET (0x0C0000000)
-#define DMM_SIZE (128)
-#define FB_OFFSET (0x41000000)
-#define PCI_MEM_TOP (0x0EFFFFFFF) // Top of PCI mem allocation region
-#define PCI_IO_TOP (0x0EFFF) // Top of PCI I/O allocation region
-#define END_OPTIONROM_SPACE (0x0DFFF) // E0000 is reserved for SystemROMs.
-
-
-#define CS5535_IDSEL (0x02000000) // IDSEL = AD25, device #15
-#define CHIPSET_DEV_NUM (15)
-#define IDSEL_BASE (11) // bit 11 = device 1
-
-
-/* standard AMD post definitions -- might as well use them. */
-#define POST_Output_Port (0x080) /* port to write post codes to*/
-
-#define POST_preSioInit (0x000) /* geode.asm*/
-#define POST_clockInit (0x001) /* geode.asm*/
-#define POST_CPURegInit (0x002) /* geode.asm*/
-#define POST_UNREAL (0x003) /* geode.asm*/
-#define POST_CPUMemRegInit (0x004) /* geode.asm*/
-#define POST_CPUTest (0x005) /* geode.asm*/
-#define POST_memSetup (0x006) /* geode.asm*/
-#define POST_memSetUpStack (0x007) /* geode.asm*/
-#define POST_memTest (0x008) /* geode.asm*/
-#define POST_shadowRom (0x009) /* geode.asm*/
-#define POST_memRAMoptimize (0x00A) /* geode.asm*/
-#define POST_cacheInit (0x00B) /* geode.asm*/
-#define POST_northBridgeInit (0x00C) /* geode.asm*/
-#define POST_chipsetInit (0x00D) /* geode.asm*/
-#define POST_sioTest (0x00E) /* geode.asm*/
-#define POST_pcATjunk (0x00F) /* geode.asm*/
-
-
-#define POST_intTable (0x010) /* geode.asm*/
-#define POST_memInfo (0x011) /* geode.asm*/
-#define POST_romCopy (0x012) /* geode.asm*/
-#define POST_PLLCheck (0x013) /* geode.asm*/
-#define POST_keyboardInit (0x014) /* geode.asm*/
-#define POST_cpuCacheOff (0x015) /* geode.asm*/
-#define POST_BDAInit (0x016) /* geode.asm*/
-#define POST_pciScan (0x017) /* geode.asm*/
-#define POST_optionRomInit (0x018) /* geode.asm*/
-#define POST_ResetLimits (0x019) /* geode.asm*/
-#define POST_summary_screen (0x01A) /* geode.asm*/
-#define POST_Boot (0x01B) /* geode.asm*/
-#define POST_SystemPreInit (0x01C) /* geode.asm*/
-#define POST_ClearRebootFlag (0x01D) /* geode.asm*/
-#define POST_GLIUInit (0x01E) /* geode.asm*/
-#define POST_BootFailed (0x01F) /* geode.asm*/
-
-
-#define POST_CPU_ID (0x020) /* cpucpuid.asm*/
-#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/
-#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/
-#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/
-#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/
-#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/
-#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/
-#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/
-#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/
-#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/
-#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/
-#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/
-#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/
-#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/
-#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/
-#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/
-
-
-
-/* PCI config*/
-#define P80_PCICFG (0x030) /* pcispace.asm*/
-
-
-/* PCI io*/
-#define P80_PCIIO (0x040) /* pcispace.asm*/
-
-
-/* PCI memory*/
-#define P80_PCIMEM (0x050) /* pcispace.asm*/
-
-
-/* SIO*/
-#define P80_SIO (0x060) /* *sio.asm*/
-
-/* Memory Setp*/
-#define P80_MEM_SETUP (0x070) /* docboot meminit*/
-#define POST_MEM_SETUP (0x070) /* memsize.asm*/
-#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/
-#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/
-#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/
-#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/
-#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/
-#define POST_MEM_ENABLE (0x076) /* memsize.asm*/
-#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/
-#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/
-#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/
-#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/
-#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/
-#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/
-#define ERROR_BANK_SET (0x07d) /* memsize.asm*/
-#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/
-#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/
-
-
-#define POST_UserPreInit (0x080) /* geode.asm*/
-#define POST_UserPostInit (0x081) /* geode.asm*/
-#define POST_Equipment_check (0x082) /* geode.asm*/
-#define POST_InitNVRAMBX (0x083) /* geode.asm*/
-#define POST_NoPIRTable (0x084) /* pci.asm*/
-#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/
-#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/
-#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/
-#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/
-#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/
-#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/
-#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/
-#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/
-#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/
-#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/
-
-
-#define POST_STACK_SETUP (0x090) /* memstack.asm*/
-#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/
-#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/
-#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/
-#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/
-#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/
-#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/
-#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/
-#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/
-
-
-#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/
-#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/
-#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/
-#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/
-#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/
-#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/
-#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/
-
-
-#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/
-#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/
-#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/
-#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/
-#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/
-#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/
-#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/
-
-
-#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/
-#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/
-#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/
-#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
-#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/
-#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/
-#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/
-#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/
-#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/
-#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/
-#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/
-#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/
-#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/
-#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/
-
-#define POST_RCONFInitError (0x0CE) /* cache.asm*/
-#define POST_CacheInitError (0x0CF) /* cache.asm*/
-
-
-#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/
-#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/
-#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/
-#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/
-#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/
-#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/
-#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/
-#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/
-#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/
-#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/
-#define POST_ROM_POSTUNCOMPRESS (0x0DE)
-
-
-#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/
-#define POST_PreChipsetInit (0x0E1) /* geode.asm*/
-#define POST_LateChipsetInit (0x0E2) /* geode.asm*/
-#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/
-
-
-#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
-
-
-/* I don't mind if somebody decides this needs to be in a seperate file. I don't see much point
- * in it, either.
- * RGM
- */
-#define Cx5535_ID ( 0x002A100B)
-#define Cx5536_ID ( 0x208F1022)
-
-/* Cs5535 as follows. */
-/* SB_GLIU*/
-/* port0 - GLIU*/
-/* port1 - GLPCI*/
-/* port2 - USB Controller #2*/
-/* port3 - ATA-5 Controller*/
-/* port4 - MDD*/
-/* port5 - AC97*/
-/* port6 - USB Controller #1*/
-/* port7 - GLCP*/
-
-
-/* SouthBridge Equates*/
-/* MSR_SB and SB_SHIFT are located in CPU.inc*/
-#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
-#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
-#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
-#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
-#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
-#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
-#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
-#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
-
-/* */
-/* GLIU*/
-/* */
-#define GLIU_SB_GLD_MSR_CAP ( MSR_SB_GLIU + 0x00)
-#define GLIU_SB_GLD_MSR_CONF ( MSR_SB_GLIU + 0x01)
-#define GLIU_SB_GLD_MSR_PM ( MSR_SB_GLIU + 0x04)
-
-/* */
-/* USB1*/
-/* */
-#define USB1_SB_GLD_MSR_CAP ( MSR_SB_USB1 + 0x00)
-#define USB1_SB_GLD_MSR_CONF ( MSR_SB_USB1 + 0x01)
-#define USB1_SB_GLD_MSR_PM ( MSR_SB_USB1 + 0x04)
-/* */
-/* USB2*/
-/* */
-#define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00)
-#define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01)
-#define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04)
-
-
-/* */
-/* ATA*/
-/* */
-#define ATA_SB_GLD_MSR_CAP ( MSR_SB_ATA + 0x00)
-#define ATA_SB_GLD_MSR_CONF ( MSR_SB_ATA + 0x01)
-#define ATA_SB_GLD_MSR_ERR ( MSR_SB_ATA + 0x03)
-#define ATA_SB_GLD_MSR_PM ( MSR_SB_ATA + 0x04)
-
-/* */
-/* AC97*/
-/* */
-#define AC97_SB_GLD_MSR_CAP ( MSR_SB_AC97 + 0x00)
-#define AC97_SB_GLD_MSR_CONF ( MSR_SB_AC97 + 0x01)
-#define AC97_SB_GLD_MSR_PM ( MSR_SB_AC97 + 0x04)
-
-/* */
-/* GLPCI*/
-/* */
-#define GLPCI_SB_GLD_MSR_CAP ( MSR_SB_GLPCI + 0x00)
-#define GLPCI_SB_GLD_MSR_CONF ( MSR_SB_GLPCI + 0x01)
-#define GLPCI_SB_GLD_MSR_PM ( MSR_SB_GLPCI + 0x04)
-#define GLPCI_SB_CTRL ( MSR_SB_GLPCI + 0x10)
-#define GLPCI_CRTL_PPIDE_SET ( 1 << 17)
-/* */
-/* GLCP*/
-/* */
-#define GLCP_SB_GLD_MSR_CAP ( MSR_SB_GLCP + 0x00)
-#define GLCP_SB_GLD_MSR_CONF ( MSR_SB_GLCP + 0x01)
-#define GLCP_SB_GLD_MSR_PM ( MSR_SB_GLCP + 0x04)
-
-/* */
-/* MDD*/
-/* */
-
-#define MDD_SMBUS (0x6000)
-#define MDD_GPIO (0x6100)
-#define MDD_MFGPT (0x6200)
-#define MDD_FLASH_BAR_0 (0x6400)
-#define MDD_FLASH_BAR_1 (0x6500)
-#define MDD_FLASH_BAR_2 (0x6600)
-#define MDD_FLASH_BAR_3 (0x6700)
-
-#define MDD_ACPI_BASE (0x9C00)
-#define MDD_PM (0x9D00)
-
-
-// # FIXME
-#define GPIO_BASE MDD_GPIO
-#define ACPI_BASE MDD_ACPI_BASE
-#define PMLogic_BASE MDD_PM
-
-
-#define MDD_SB_GLD_MSR_CAP ( MSR_SB_MDD + 0x00)
-#define MDD_SB_GLD_MSR_CONF ( MSR_SB_MDD + 0x01)
-#define MDD_SB_GLD_MSR_PM ( MSR_SB_MDD + 0x04)
-#define LBAR_EN ( 0x01)
-#define IO_MASK ( 0x1f)
-#define MEM_MASK ( 0x0FFFFF)
-#define MDD_LBAR_IRQ ( MSR_SB_MDD + 0x08)
-#define MDD_LBAR_KEL1 ( MSR_SB_MDD + 0x09)
-#define MDD_LBAR_KEL2 ( MSR_SB_MDD + 0x0A)
-#define MDD_LBAR_SMB ( MSR_SB_MDD + 0x0B)
-#define MDD_LBAR_GPIO ( MSR_SB_MDD + 0x0C)
-#define MDD_LBAR_MFGPT ( MSR_SB_MDD + 0x0D)
-#define MDD_LBAR_ACPI ( MSR_SB_MDD + 0x0E)
-#define MDD_LBAR_PMS ( MSR_SB_MDD + 0x0F)
-
-#define MDD_LBAR_FLSH0 ( MSR_SB_MDD + 0x010)
-#define MDD_LBAR_FLSH1 ( MSR_SB_MDD + 0x011)
-#define MDD_LBAR_FLSH2 ( MSR_SB_MDD + 0x012)
-#define MDD_LBAR_FLSH3 ( MSR_SB_MDD + 0x013)
-#define MDD_LEG_IO ( MSR_SB_MDD + 0x014)
-#define MDD_PIN_OPT ( MSR_SB_MDD + 0x015)
-#define MDD_SOFT_IRQ ( MSR_SB_MDD + 0x016)
-#define MDD_SOFT_RESET ( MSR_SB_MDD + 0x017)
-#define MDD_NORF_CNTRL ( MSR_SB_MDD + 0x018)
-#define MDD_NORF_T01 ( MSR_SB_MDD + 0x019)
-#define MDD_NORF_T23 ( MSR_SB_MDD + 0x01A)
-#define MDD_NANDF_DATA ( MSR_SB_MDD + 0x01B)
-#define MDD_NADF_CNTL ( MSR_SB_MDD + 0x01C)
-#define MDD_AC_DMA ( MSR_SB_MDD + 0x01E)
-#define MDD_KEL_CNTRL ( MSR_SB_MDD + 0x01F)
-
-#define MDD_IRQM_YLOW ( MSR_SB_MDD + 0x020)
-#define MDD_IRQM_YHIGH ( MSR_SB_MDD + 0x021)
-#define MDD_IRQM_ZLOW ( MSR_SB_MDD + 0x022)
-#define MDD_IRQM_ZHIGH ( MSR_SB_MDD + 0x023)
-#define MDD_IRQM_PRIM ( MSR_SB_MDD + 0x024)
-#define MDD_IRQM_LPC ( MSR_SB_MDD + 0x025)
-#define MDD_IRQM_LXIRR ( MSR_SB_MDD + 0x026)
-#define MDD_IRQM_HXIRR ( MSR_SB_MDD + 0x027)
-
-#define MDD_MFGPT_IRQ ( MSR_SB_MDD + 0x028)
-#define MDD_MFGPT_NR ( MSR_SB_MDD + 0x029)
-#define MDD_MFGPT_RES0 ( MSR_SB_MDD + 0x02A)
-#define MDD_MFGPT_RES1 ( MSR_SB_MDD + 0x02B)
-
-#define MDD_FLOP_S3F2 ( MSR_SB_MDD + 0x030)
-#define MDD_FLOP_S3F7 ( MSR_SB_MDD + 0x031)
-#define MDD_FLOP_S372 ( MSR_SB_MDD + 0x032)
-#define MDD_FLOP_S377 ( MSR_SB_MDD + 0x033)
-
-#define MDD_PIC_S ( MSR_SB_MDD + 0x034)
-#define MDD_PIT_S ( MSR_SB_MDD + 0x036)
-#define MDD_PIT_CNTRL ( MSR_SB_MDD + 0x037)
-
-#define MDD_UART1_MOD ( MSR_SB_MDD + 0x038)
-#define MDD_UART1_DON ( MSR_SB_MDD + 0x039)
-#define MDD_UART1_CONF ( MSR_SB_MDD + 0x03A)
-#define MDD_UART2_MOD ( MSR_SB_MDD + 0x03C)
-#define MDD_UART2_DON ( MSR_SB_MDD + 0x03D)
-#define MDD_UART2_CONF ( MSR_SB_MDD + 0x03E)
-
-#define MDD_DMA_MAP ( MSR_SB_MDD + 0x040)
-#define MDD_DMA_SHAD1 ( MSR_SB_MDD + 0x041)
-#define MDD_DMA_SHAD2 ( MSR_SB_MDD + 0x042)
-#define MDD_DMA_SHAD3 ( MSR_SB_MDD + 0x043)
-#define MDD_DMA_SHAD4 ( MSR_SB_MDD + 0x044)
-#define MDD_DMA_SHAD5 ( MSR_SB_MDD + 0x045)
-#define MDD_DMA_SHAD6 ( MSR_SB_MDD + 0x046)
-#define MDD_DMA_SHAD7 ( MSR_SB_MDD + 0x047)
-#define MDD_DMA_SHAD8 ( MSR_SB_MDD + 0x048)
-#define MDD_DMA_SHAD9 ( MSR_SB_MDD + 0x049)
-
-#define MDD_LPC_EADDR ( MSR_SB_MDD + 0x04C)
-#define MDD_LPC_ESTAT ( MSR_SB_MDD + 0x04D)
-#define MDD_LPC_SIRQ ( MSR_SB_MDD + 0x04E)
-#define MDD_LPC_RES ( MSR_SB_MDD + 0x04F)
-
-#define MDD_PML_TMR ( MSR_SB_MDD + 0x050)
-#define MDD_RTC_RAM_LO_CK ( MSR_SB_MDD + 0x054)
-#define MDD_RTC_DOMA_IND ( MSR_SB_MDD + 0x055)
-#define MDD_RTC_MONA_IND ( MSR_SB_MDD + 0x056)
-#define MDD_RTC_CENTURY_OFFSET ( MSR_SB_MDD + 0x057)
-
-/* ***********************************************************/
-/* LBUS Device Equates - */
-/* ***********************************************************/
-
-/* */
-/* SMBus*/
-/* */
-
-#define SMBUS_SMBSDA ( SMBUS_BASE + 0x00)
-#define SMBUS_SMBST ( SMBUS_BASE + 0x01)
-#define SMBST_SLVSTP_SET ( 1 << 7)
-#define SMBST_SDAST_SET ( 1 << 6)
-#define SMBST_BER_SET ( 1 << 5)
-#define SMBST_NEGACK_SET ( 1 << 4)
-#define SMBST_STASTR_SET ( 1 << 3)
-#define SMBST_NMATCH_SET ( 1 << 2)
-#define SMBST_MASTER_SET ( 1 << 1)
-#define SMBST_XMIT_SET ( 1 << 0)
-#define SMBUS_SMBCST ( SMBUS_BASE + 0x02)
-#define SMBCST_TGSCL_SET ( 1 << 5)
-#define SMBCST_TSDA_SET ( 1 << 4)
-#define SMBCST_GCMTCH_SET ( 1 << 3)
-#define SMBCST_MATCH_SET ( 1 << 2)
-#define SMBCST_BB_SET ( 1 << 1)
-#define SMBCST_BUSY_SET ( 1 << 0)
-#define SMBUS_SMBCTL1 ( SMBUS_BASE + 0x03)
-#define SMBCTL1_STASTRE_SET ( 1 << 7)
-#define SMBCTL1_NMINTE_SET ( 1 << 6)
-#define SMBCTL1_GCMEN_SET ( 1 << 5)
-#define SMBCTL1_RECACK_SET ( 1 << 4)
-#define SMBCTL1_DMAEN_SET ( 1 << 3)
-#define SMBCTL1_INTEN_SET ( 1 << 2)
-#define SMBCTL1_STOP_SET ( 1 << 1)
-#define SMBCTL1_START_SET ( 1 << 0)
-#define SMBUS_SMBADDR ( SMBUS_BASE + 0x04)
-#define SMBADDR_SAEN_SET ( 1 << 7)
-#define SMBUS_SMBCTL2 ( SMBUS_BASE + 0x05)
-#define SMBCTL2_SCLFRQ_SHIFT ( 1 << 1)
-#define SMBCTL2_ENABLE_SET ( 1 << 0)
-
-/* */
-/* GPIO*/
-/* */
-
-#define GPIOL_0_SET ( 1 << 0)
-#define GPIOL_1_SET ( 1 << 1)
-#define GPIOL_2_SET ( 1 << 2)
-#define GPIOL_3_SET ( 1 << 3)
-#define GPIOL_4_SET ( 1 << 4)
-#define GPIOL_5_SET ( 1 << 5)
-#define GPIOL_6_SET ( 1 << 6)
-#define GPIOL_7_SET ( 1 << 7)
-#define GPIOL_8_SET ( 1 << 8)
-#define GPIOL_9_SET ( 1 << 9)
-#define GPIOL_10_SET ( 1 << 10)
-#define GPIOL_11_SET ( 1 << 11)
-#define GPIOL_12_SET ( 1 << 12)
-#define GPIOL_13_SET ( 1 << 13)
-#define GPIOL_14_SET ( 1 << 14)
-#define GPIOL_15_SET ( 1 << 15)
-
-#define GPIOL_0_CLEAR ( 1 << 16)
-#define GPIOL_1_CLEAR ( 1 << 17)
-#define GPIOL_2_CLEAR ( 1 << 18)
-#define GPIOL_3_CLEAR ( 1 << 19)
-#define GPIOL_4_CLEAR ( 1 << 20)
-#define GPIOL_5_CLEAR ( 1 << 21)
-#define GPIOL_6_CLEAR ( 1 << 22)
-#define GPIOL_7_CLEAR ( 1 << 23)
-#define GPIOL_8_CLEAR ( 1 << 24)
-#define GPIOL_9_CLEAR ( 1 << 25)
-#define GPIOL_10_CLEAR ( 1 << 26)
-#define GPIOL_11_CLEAR ( 1 << 27)
-#define GPIOL_12_CLEAR ( 1 << 28)
-#define GPIOL_13_CLEAR ( 1 << 29)
-#define GPIOL_14_CLEAR ( 1 << 30)
-#define GPIOL_15_CLEAR ( 1 << 31)
-
-#define GPIOH_16_SET ( 1 << 0)
-#define GPIOH_17_SET ( 1 << 1)
-#define GPIOH_18_SET ( 1 << 2)
-#define GPIOH_19_SET ( 1 << 3)
-#define GPIOH_20_SET ( 1 << 4)
-#define GPIOH_21_SET ( 1 << 5)
-#define GPIOH_22_SET ( 1 << 6)
-#define GPIOH_23_SET ( 1 << 7)
-#define GPIOH_24_SET ( 1 << 8)
-#define GPIOH_25_SET ( 1 << 9)
-#define GPIOH_26_SET ( 1 << 10)
-#define GPIOH_27_SET ( 1 << 11)
-#define GPIOH_28_SET ( 1 << 12)
-#define GPIOH_29_SET ( 1 << 13)
-#define GPIOH_30_SET ( 1 << 14)
-#define GPIOH_31_SET ( 1 << 15)
-
-#define GPIOH_16_CLEAR ( 1 << 16)
-#define GPIOH_17_CLEAR ( 1 << 17)
-#define GPIOH_18_CLEAR ( 1 << 18)
-#define GPIOH_19_CLEAR ( 1 << 19)
-#define GPIOH_20_CLEAR ( 1 << 20)
-#define GPIOH_21_CLEAR ( 1 << 21)
-#define GPIOH_22_CLEAR ( 1 << 22)
-#define GPIOH_23_CLEAR ( 1 << 23)
-#define GPIOH_24_CLEAR ( 1 << 24)
-#define GPIOH_25_CLEAR ( 1 << 25)
-#define GPIOH_26_CLEAR ( 1 << 26)
-#define GPIOH_27_CLEAR ( 1 << 27)
-#define GPIOH_28_CLEAR ( 1 << 28)
-#define GPIOH_29_CLEAR ( 1 << 29)
-#define GPIOH_30_CLEAR ( 1 << 30)
-#define GPIOH_31_CLEAR ( 1 << 31)
-
-
-/* GPIO LOW Bank Bit Registers*/
-#define GPIOL_OUTPUT_VALUE ( GPIO_BASE + 0x00)
-#define GPIOL_OUTPUT_ENABLE ( GPIO_BASE + 0x04)
-#define GPIOL_OUT_OPENDRAIN ( GPIO_BASE + 0x08)
-#define GPIOL_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x0C)
-#define GPIOL_OUT_AUX1_SELECT ( GPIO_BASE + 0x10)
-#define GPIOL_OUT_AUX2_SELECT ( GPIO_BASE + 0x14)
-#define GPIOL_PULLUP_ENABLE ( GPIO_BASE + 0x18)
-#define GPIOL_PULLDOWN_ENABLE ( GPIO_BASE + 0x1C)
-#define GPIOL_INPUT_ENABLE ( GPIO_BASE + 0x20)
-#define GPIOL_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x24)
-#define GPIOL_IN_FILTER_ENABLE ( GPIO_BASE + 0x28)
-#define GPIOL_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x2C)
-#define GPIOL_READ_BACK ( GPIO_BASE + 0x30)
-#define GPIOL_IN_AUX1_SELECT ( GPIO_BASE + 0x34)
-#define GPIOL_EVENTS_ENABLE ( GPIO_BASE + 0x38)
-#define GPIOL_LOCK_ENABLE ( GPIO_BASE + 0x3C)
-#define GPIOL_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x40)
-#define GPIOL_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x44)
-#define GPIOL_IN_POSEDGE_STATUS ( GPIO_BASE + 0x48)
-#define GPIOL_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x4C)
-
-/* GPIO High Bank Bit Registers*/
-#define GPIOH_OUTPUT_VALUE ( GPIO_BASE + 0x80)
-#define GPIOH_OUTPUT_ENABLE ( GPIO_BASE + 0x84)
-#define GPIOH_OUT_OPENDRAIN ( GPIO_BASE + 0x88)
-#define GPIOH_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x8C)
-#define GPIOH_OUT_AUX1_SELECT ( GPIO_BASE + 0x90)
-#define GPIOH_OUT_AUX2_SELECT ( GPIO_BASE + 0x94)
-#define GPIOH_PULLUP_ENABLE ( GPIO_BASE + 0x98)
-#define GPIOH_PULLDOWN_ENABLE ( GPIO_BASE + 0x9C)
-#define GPIOH_INPUT_ENABLE ( GPIO_BASE + 0x0A0)
-#define GPIOH_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x0A4)
-#define GPIOH_IN_FILTER_ENABLE ( GPIO_BASE + 0x0A8)
-#define GPIOH_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x0AC)
-#define GPIOH_READ_BACK ( GPIO_BASE + 0x0B0)
-#define GPIOH_IN_AUX1_SELECT ( GPIO_BASE + 0x0B4)
-#define GPIOH_EVENTS_ENABLE ( GPIO_BASE + 0x0B8)
-#define GPIOH_LOCK_ENABLE ( GPIO_BASE + 0x0BC)
-#define GPIOH_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x0C0)
-#define GPIOH_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x0C4)
-#define GPIOH_IN_POSEDGE_STATUS ( GPIO_BASE + 0x0C8)
-#define GPIOH_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x0CC)
-
-/* Input Conditioning Function Registers*/
-#define GPIO_00_FILTER_AMOUNT ( GPIO_BASE + 0x50)
-#define GPIO_00_FILTER_COUNT ( GPIO_BASE + 0x52)
-#define GPIO_00_EVENT_COUNT ( GPIO_BASE + 0x54)
-#define GPIO_00_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x56)
-#define GPIO_01_FILTER_AMOUNT ( GPIO_BASE + 0x58)
-#define GPIO_01_FILTER_COUNT ( GPIO_BASE + 0x5A)
-#define GPIO_01_EVENT_COUNT ( GPIO_BASE + 0x5C)
-#define GPIO_01_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x5E)
-#define GPIO_02_FILTER_AMOUNT ( GPIO_BASE + 0x60)
-#define GPIO_02_FILTER_COUNT ( GPIO_BASE + 0x62)
-#define GPIO_02_EVENT_COUNT ( GPIO_BASE + 0x64)
-#define GPIO_02_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x66)
-#define GPIO_03_FILTER_AMOUNT ( GPIO_BASE + 0x68)
-#define GPIO_03_FILTER_COUNT ( GPIO_BASE + 0x6A)
-#define GPIO_03_EVENT_COUNT ( GPIO_BASE + 0x6C)
-#define GPIO_03_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x6E)
-#define GPIO_04_FILTER_AMOUNT ( GPIO_BASE + 0x70)
-#define GPIO_04_FILTER_COUNT ( GPIO_BASE + 0x72)
-#define GPIO_04_EVENT_COUNT ( GPIO_BASE + 0x74)
-#define GPIO_04_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x76)
-#define GPIO_05_FILTER_AMOUNT ( GPIO_BASE + 0x78)
-#define GPIO_05_FILTER_COUNT ( GPIO_BASE + 0x7A)
-#define GPIO_05_EVENT_COUNT ( GPIO_BASE + 0x7C)
-#define GPIO_05_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x7E)
-#define GPIO_06_FILTER_AMOUNT ( GPIO_BASE + 0x0D0)
-#define GPIO_06_FILTER_COUNT ( GPIO_BASE + 0x0D2)
-#define GPIO_06_EVENT_COUNT ( GPIO_BASE + 0x0D4)
-#define GPIO_06_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0D6)
-#define GPIO_07_FILTER_AMOUNT ( GPIO_BASE + 0x0D8)
-#define GPIO_07_FILTER_COUNT ( GPIO_BASE + 0x0DA)
-#define GPIO_07_EVENT_COUNT ( GPIO_BASE + 0x0DC)
-#define GPIO_07_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0DE)
-
-/* R/W GPIO Interrupt &PME Mapper Registers*/
-#define GPIO_MAPPER_X ( GPIO_BASE + 0x0E0)
-#define GPIO_MAPPER_Y ( GPIO_BASE + 0x0E4)
-#define GPIO_MAPPER_Z ( GPIO_BASE + 0x0E8)
-#define GPIO_MAPPER_W ( GPIO_BASE + 0x0EC)
-#define GPIO_FE_SELECT_0 ( GPIO_BASE + 0x0F0)
-#define GPIO_FE_SELECT_1 ( GPIO_BASE + 0x0F1)
-#define GPIO_FE_SELECT_2 ( GPIO_BASE + 0x0F2)
-#define GPIO_FE_SELECT_3 ( GPIO_BASE + 0x0F3)
-#define GPIO_FE_SELECT_4 ( GPIO_BASE + 0x0F4)
-#define GPIO_FE_SELECT_5 ( GPIO_BASE + 0x0F5)
-#define GPIO_FE_SELECT_6 ( GPIO_BASE + 0x0F6)
-#define GPIO_FE_SELECT_7 ( GPIO_BASE + 0x0F7)
-
-/* Event Counter Decrement Registers*/
-#define GPIOL_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0F8)
-#define GPIOH_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0FC)
-
-/* This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/
-#define FUNC0 ( 0x90)
-
-
-/* sworley, PMC register*/
-#define PM_SSD ( PMLogic_BASE + 0x00)
-#define PM_SCXA ( PMLogic_BASE + 0x04)
-#define PM_SCYA ( PMLogic_BASE + 0x08)
-#define PM_SODA ( PMLogic_BASE + 0x0C)
-#define PM_SCLK ( PMLogic_BASE + 0x10)
-#define PM_SED ( PMLogic_BASE + 0x14)
-#define PM_SCXD ( PMLogic_BASE + 0x18)
-#define PM_SCYD ( PMLogic_BASE + 0x1C)
-#define PM_SIDD ( PMLogic_BASE + 0x20)
-#define PM_WKD ( PMLogic_BASE + 0x30)
-#define PM_WKXD ( PMLogic_BASE + 0x34)
-#define PM_RD ( PMLogic_BASE + 0x38)
-#define PM_WKXA ( PMLogic_BASE + 0x3C)
-#define PM_FSD ( PMLogic_BASE + 0x40)
-#define PM_TSD ( PMLogic_BASE + 0x44)
-#define PM_PSD ( PMLogic_BASE + 0x48)
-#define PM_NWKD ( PMLogic_BASE + 0x4C)
-#define PM_AWKD ( PMLogic_BASE + 0x50)
-#define PM_SSC ( PMLogic_BASE + 0x54)
-
-
-/* FLASH device macros */
-#define FLASH_TYPE_NONE 0 /* No flash device installed */
-#define FLASH_TYPE_NAND 1 /* NAND device */
-#define FLASH_TYPE_NOR 2 /* NOR device */
-
-#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
-#define FLASH_IF_IO 2 /* I/O interface for Flash device */
-
-/* Flash Memory Mask values */
-#define FLASH_MEM_DEFAULT 0x00000000
-#define FLASH_MEM_4K 0xFFFFF000
-#define FLASH_MEM_8K 0xFFFFE000
-#define FLASH_MEM_16K 0xFFFFC000
-#define FLASH_MEM_128K 0xFFFE0000
-#define FLASH_MEM_512K 0xFFFC0000
-#define FLASH_MEM_4M 0xFFC00000
-#define FLASH_MEM_8M 0xFF800000
-#define FLASH_MEM_16M 0xFF000000
-
-/* Flash IO Mask values */
-#define FLASH_IO_DEFAULT 0x00000000
-#define FLASH_IO_16B 0x0000FFF0
-#define FLASH_IO_32B 0x0000FFE0
-#define FLASH_IO_64B 0x0000FFC0
-#define FLASH_IO_128B 0x0000FF80
-#define FLASH_IO_256B 0x0000FF00
-
-
-
-#endif /* CPU_AMD_LXDEF_H */
+#endif
diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h
index 0626545336..286eaa94c5 100644
--- a/src/include/cpu/amd/vr.h
+++ b/src/include/cpu/amd/vr.h
@@ -1,22 +1,11 @@
-/* <LIC_AMD_STD>
- * Copyright (C) 2003-2005 Advanced Micro Devices, Inc. All Rights Reserved.
- * </LIC_AMD_STD> */
-//<CTL_AMD_STD>
-//$Id: //bios/main/vsa_ii/inc/vr.h#18 $
-//$Header: //bios/main/vsa_ii/inc/vr.h#18 $
-//$Date: 2005/09/29 $
-//$DateTime: 2005/09/29 11:07:14 $
-//$Change: 65425 $
-//$File: //bios/main/vsa_ii/inc/vr.h $
-//$Revision: #18 $
-//$Author: johnk $
-//</CTL_AMD_STD>
-//<DOC_AMD_STD>
-// Virtual Register USAGE:
-//
-// Index: AH = Class, AL = Parameter_ID
-// Data: AX = data
-//</DOC_AMD_STD>
+/*
+*
+* Copyright (C) 2007 Advanced Micro Devices
+*
+*/
+
+#ifndef CPU_AMD_VR_H
+#define CPU_AMD_VR_H
#define VRC_INDEX 0xAC1C // Index register
#define VRC_DATA 0xAC1E // Data register
@@ -484,3 +473,28 @@
#define MAX_THERMAL VRC_THERMAL_SMB_DATA
#define MAX_VR_CLASS VRC_THERMAL
+
+/*
+ * Write to a Virtual Register
+ * AX = Class/Index
+ * CX = data to write
+ */
+static inline void vrWrite(uint16_t wClassIndex, uint16_t wData)
+{
+ outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+ outw(wData, VRC_DATA);
+}
+
+ /*
+ * Read from a Virtual Register
+ * AX = Class/Index
+ * Returns a 16-bit word of data
+ */
+static inline uint16_t vrRead(uint16_t wClassIndex)
+{
+ uint16_t wData;
+ outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+ wData = inw(VRC_DATA);
+ return wData;
+}
+#endif
diff --git a/src/include/spd.h b/src/include/spd.h
index 6703ef2845..b0c00ff094 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -85,6 +85,17 @@
#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */
#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
+/* DRAM specifications use the following naming conventions for SPD locations */
+#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME
+#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE
+#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY
+#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
+#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE
+#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME
+#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
+#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
+
+
/* SPD_MEMORY_TYPE values. */
#define SPD_MEMORY_TYPE_FPM_DRAM 1
#define SPD_MEMORY_TYPE_EDO 2
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 17:38:50 +0000