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authorDuncan Laurie <dlaurie@chromium.org>2015-02-19 16:21:10 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-18 08:52:59 +0200
commitaafdddfc3825580ecf1b73f0e423b5637e27e556 (patch)
tree113aeda1a83236d610a1ca221051e52de5e33756
parent2f2a5e54a7614f16169718a90c7cf059ac4165e4 (diff)
broadwell: Disable XHCI compliance mode entry
To avoid entries with Type-C alternate mode devices disable compliance mode entry. This needs to be set on both boot and resume. BUG=chrome-os-partner:35320 BRANCH=samus TEST=manual: 1) boot on samus with USB keyboard plugged in -> controller in D0 at boot 2) iotools mmio_read32 0xe12080ec == 0x18010c01 3) suspend and resume 4) iotools mmio_read32 0xe12080ec == 0x18010c01 5) remove USB keyboard -> controller in D3 6) iotools mmio_read32 0xe12080ec == 0xffffffff 7) plug in USB keyboard -> controller in D0 8) iotools mmio_read32 0xe12080ec == 0x18010c01 9) boot with no external USB devices -> controller in D3 at boot 10) iotools mmio_read32 0xe12080ec == 0xffffffff 11) plug in USB keyboard -> controller in D0 12) iotools mmio_read32 0xe12080ec == 0x18010c01 Change-Id: I4d566112b3c188bafdf9a4bbd92944c89500e3e8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db8c8ab8ff25f6a39cd50dcc91b5ba9fd7d05059 Original-Change-Id: I8b68ba75e254a7e236c869f4470207eb5290053d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251361 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9782 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/intel/broadwell/xhci.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 4c721c28a3..fde8bf7cd6 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -192,11 +192,30 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
}
#else /* !__SMM__ */
+static void xhci_init(struct device *dev)
+{
+ struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ u16 reg16;
+ u32 reg32;
+
+ /* Ensure controller is in D0 state */
+ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
+ reg16 &= ~XHCI_PWR_CTL_SET_MASK;
+ reg16 |= XHCI_PWR_CTL_SET_D0;
+ pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
+
+ /* Disable Compliance Mode Entry */
+ reg32 = read32(res2mmio(res, 0x80ec, 0));
+ reg32 |= (1 << 0);
+ write32(res2mmio(res, 0x80ec, 0), reg32);
+}
+
static struct device_operations usb_xhci_ops = {
.read_resources = &pci_dev_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.ops_pci = &broadwell_pci_ops,
+ .init = &xhci_init,
};
static const unsigned short pci_device_ids[] = {