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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-18 05:07:47 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-30 03:01:03 +0000
commit91bc620702bf18c5dcbeb9f4f4a91305398b16f4 (patch)
tree9ecf04096454f543c9022dcdc96341ea94e9ed22
parente0c084cab362c5b53df8c33d20a74d41ee519504 (diff)
intel/quark: Use common romstage entry
Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/soc/intel/quark/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c8
2 files changed, 2 insertions, 7 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index be5b320351..13963d4b23 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -22,5 +22,6 @@ romstage-y += mtrr.c
romstage-y += pcie.c
romstage-y += report_platform.c
romstage-y += romstage.c
+romstage-y += ../../../../cpu/intel/car/romstage.c
postcar-y += mtrr.c
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index b3f3ee8cb6..6e23de7039 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <arch/symbols.h>
#include <console/console.h>
@@ -28,9 +27,7 @@
#include <soc/reg_access.h>
#include <soc/storage_test.h>
-static struct postcar_frame early_mtrrs;
-
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
bool s3wake;
@@ -61,9 +58,6 @@ asmlinkage void car_stage_entry(void)
/* Initialize the PCIe bridges */
pcie_init();
-
- prepare_and_run_postcar(&early_mtrrs);
- /* We do not return here. */
}
static struct chipset_power_state power_state;