diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-17 18:28:29 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 18:10:51 +0000 |
| commit | 8cb8374e3c8b3236527796df210ac3d6bbaf3065 (patch) | |
| tree | 25df04cbfafb097c4a5a2da80cc29c5af867a849 | |
| parent | 5d92aa5882c13dd11fe6fa155d2dea3371856871 (diff) | |
sb/intel/lynxpoint: Drop space after casts
Casts can be considered unary operators, so drop the space.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/sata.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b378..ce1b109342 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -14,7 +14,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) acpi_header_t *header = &(hpet->header); acpi_addr_t *addr = &(hpet->addr); - memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); /* fill out header fields */ memcpy(header->signature, "HPET", 4); @@ -37,7 +37,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet) hpet->min_tick = 0x0080; header->checksum = - acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); + acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs) @@ -66,7 +66,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt) memcpy(&ssdt->asl_compiler_id, ASLC, 4); ssdt->asl_compiler_revision = asl_revision; ssdt->length = sizeof(acpi_header_t); - acpigen_set_current((char *) current); + acpigen_set_current((char *)current); /* Fill the SSDT with an entry for each SerialIO device */ for (id = 0; id < 8; id++) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 956d1d24de..6a5dd40644 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -108,7 +108,7 @@ int early_pch_init(void) RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ - (void) RCBA16(OIC); + (void)RCBA16(OIC); /* Mainboard RCBA settings */ mainboard_config_rcba(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index fad83b1612..a161087302 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -715,7 +715,7 @@ void southbridge_inject_dsdt(const struct device *dev) /* Add it to DSDT. */ acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (u32)gnvs); acpigen_pop_len(); } } @@ -748,7 +748,7 @@ static unsigned long southbridge_write_acpi_tables(const struct device *device, */ printk(BIOS_DEBUG, "ACPI: * HPET\n"); - hpet = (acpi_hpet_t *) current; + hpet = (acpi_hpet_t *)current; current += sizeof(acpi_hpet_t); current = acpi_align_current(current); acpi_create_intel_hpet(hpet); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 57824dfe90..308d3c32ce 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -149,8 +149,8 @@ static void sata_init(struct device *dev) write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x03, config->sata_port_map); - (void) read32(abar + 0x03); /* Read back 1 */ - (void) read32(abar + 0x03); /* Read back 2 */ + (void)read32(abar + 0x03); /* Read back 1 */ + (void)read32(abar + 0x03); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x09); /* Enable DEVSLP */ |