mediatek/mt8183: Add SPI GPIO driving setting

Set SPI GPIO driving to support SPI FLASH.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: I95002ec71abd751c33c089185db04ed4a8686699
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32460
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 61 insertions, 0 deletions

diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c
index 9d6c38ba64..9a7e71c292 100644
--- a/src/mainboard/google/kukui/bootblock.c
+++ b/src/mainboard/google/kukui/bootblock.c
@@ -15,9 +15,12 @@
 
 #include <bootblock_common.h>
 #include <soc/spi.h>
+#include <soc/gpio.h>
 
 void bootblock_mainboard_init(void)
 {
 	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz);
 	mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz);
+	gpio_set_spi_driving(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK,
+			     10);
 }
diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c
index 327d389eb2..3eccfbd50d 100644
--- a/src/soc/mediatek/mt8183/gpio.c
+++ b/src/soc/mediatek/mt8183/gpio.c
@@ -15,11 +15,15 @@
 
 #include <device/mmio.h>
 #include <gpio.h>
+#include <assert.h>
+#include <soc/spi.h>
 
 enum {
 	EN_OFFSET = 0x60,
 	SEL_OFFSET = 0x80,
 	EH_RSEL_OFFSET = 0xF0,
+	GPIO_DRV0_OFFSET = 0xA0,
+	GPIO_DRV1_OFFSET = 0XB0,
 };
 
 static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
@@ -128,3 +132,54 @@ void gpio_set_i2c_eh_rsel(void)
 		I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5),
 		I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5));
 }
+
+void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
+			  unsigned int milliamps)
+{
+	void *reg = NULL;
+	unsigned int reg_val = milliamps / 2 - 1, offset = 0;
+
+	assert(bus < SPI_BUS_NUMBER);
+	assert(milliamps >= 2 && milliamps <= 16);
+	assert(pad_select <= SPI_PAD1_MASK);
+
+	switch (bus) {
+	case 0:
+		reg = (void *)(IOCFG_RB_BASE + GPIO_DRV1_OFFSET);
+		offset = 0;
+		break;
+	case 1:
+		if (pad_select == SPI_PAD0_MASK) {
+			reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET);
+			offset = 0;
+		} else if (pad_select == SPI_PAD1_MASK) {
+			clrsetbits_le32((void *)IOCFG_RM_BASE +
+					GPIO_DRV0_OFFSET, 0xf | 0xf << 20,
+					reg_val | reg_val << 20);
+			clrsetbits_le32((void *)IOCFG_RM_BASE +
+					GPIO_DRV1_OFFSET, 0xf << 16,
+					reg_val << 16);
+			return;
+		}
+		break;
+	case 2:
+		clrsetbits_le32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET,
+				0xf << 8 | 0xf << 12,
+				reg_val << 8 | reg_val << 12);
+		return;
+	case 3:
+		reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET);
+		offset = 16;
+		break;
+	case 4:
+		reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET);
+		offset = 12;
+		break;
+	case 5:
+		reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET);
+		offset = 8;
+		break;
+	}
+
+	clrsetbits_le32(reg, 0xf << offset, reg_val << offset);
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h
index 5a98953974..a0d6262abb 100644
--- a/src/soc/mediatek/mt8183/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8183/include/soc/gpio.h
@@ -19,6 +19,7 @@
 #include <soc/addressmap.h>
 #include <soc/gpio_common.h>
 #include <types.h>
+#include <soc/spi_common.h>
 
 enum {
 	MAX_GPIO_REG_BITS = 32,
@@ -617,5 +618,7 @@ check_member(gpio_regs, mode[22].val, 0x460);
 
 static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
 void gpio_set_i2c_eh_rsel(void);
+void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
+			  unsigned int milliamps);
 
 #endif