diff options
| author | Furquan Shaikh <furquan@google.com> | 2015-07-10 15:27:02 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-13 10:00:25 +0200 |
| commit | 8799fde76062b381721ad856fb382983b98c52a5 (patch) | |
| tree | 1b520edc9bbf893fc1befe8dbb8d6d9a34c16700 | |
| parent | 6df355da879797899eb6337eb21868163c1ee07d (diff) | |
arm64/a57: Move cortex_a57.h under include directory
BUG=chrome-os-partner:41877
BRANCH=None
TEST=Compiles successfully
Change-Id: I8a94176a3faacb25ae5e9eaeaac4011ddf5af6a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 802cba6f28a4e683256e8ce9fb6395acecdc9397
Original-Change-Id: I3a5983d4a40466bc0aa8ab3bd8430ab6cdd093cc
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284868
Original-Reviewed-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10898
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/arch/arm64/cpu/cortex_a57.S | 2 | ||||
| -rw-r--r-- | src/arch/arm64/include/cpu/cortex_a57.h (renamed from src/arch/arm64/cpu/cortex_a57.h) | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/arm64/cpu/cortex_a57.S b/src/arch/arm64/cpu/cortex_a57.S index ce8534b0a7..4535d2bb5e 100644 --- a/src/arch/arm64/cpu/cortex_a57.S +++ b/src/arch/arm64/cpu/cortex_a57.S @@ -19,7 +19,7 @@ #include <arch/asm.h> #include <arch/cache_helpers.h> -#include "cortex_a57.h" +#include <cpu/cortex_a57.h> ENTRY(arm64_cpu_early_setup) mrs x0, CPUECTLR_EL1 diff --git a/src/arch/arm64/cpu/cortex_a57.h b/src/arch/arm64/include/cpu/cortex_a57.h index 5bd6160d18..113a6ff946 100644 --- a/src/arch/arm64/cpu/cortex_a57.h +++ b/src/arch/arm64/include/cpu/cortex_a57.h @@ -20,6 +20,9 @@ #ifndef __ARCH_ARM64_CORTEX_A57_H__ #define __ARCH_ARM64_CORTEX_A57_H__ +#define CPUACTLR_EL1 s3_1_c15_c2_0 +#define BTB_INVALIDATE (1 << 0) + #define CPUECTLR_EL1 S3_1_c15_c2_1 #define SMPEN_SHIFT 6 |