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authorDuncan Laurie <dlaurie@chromium.org>2013-05-22 09:51:11 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-25 23:37:05 +0100
commit7fab00c8976bae54ed32617dd1e4c9b0ace249ab (patch)
tree66a9cefa37e8acdb2b6d5f8dda6c4b1fa9ccf5c6
parent98c40622feeaf1d8f211501e8f337d5bde544d13 (diff)
lynxpoint: Fix XHCI controller device in ACPI
The ACPI code was defining two EHCI controllers and ignoring the XHCI controller. This changes the second EHCI controller to be XHCI instead and changes the wake resource to indicate S3 and not S4. cat /proc/acpi/wakeup Device S-state Status Sysfs node HDEF S4 *disabled pci:0000:00:1b.0 EHCI S3 *enabled pci:0000:00:1d.0 XHCI S3 *enabled pci:0000:00:14.0 Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4181 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/usb.asl12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl
index cf3e6a049f..5c1f6a57a5 100644
--- a/src/southbridge/intel/lynxpoint/acpi/usb.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl
@@ -23,11 +23,11 @@
// EHCI Controller 0:1d.0
-Device (EHC1)
+Device (EHCI)
{
Name(_ADR, 0x001d0000)
- Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+ Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
// Leave USB ports on for to allow Wake from USB
@@ -55,13 +55,13 @@ Device (EHC1)
}
}
-// EHCI #2 Controller 0:1a.0
+// XHCI Controller 0:14.0
-Device (EHC2)
+Device (XHCI)
{
- Name(_ADR, 0x001a0000)
+ Name(_ADR, 0x00140000)
- Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+ Name (_PRW, Package(){ 13, 3 }) // Power Resources for Wake
// Leave USB ports on for to allow Wake from USB