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| author | Florian Zumbiehl <florz@florz.de> | 2011-11-01 20:17:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-07 11:40:55 +0100 |
| commit | 7e9de01c4758cc1e8adb05d0c443701495e98fe0 (patch) | |
| tree | 7309778741f5ab74fb7c034a40245008c716a3bf | |
| parent | 643c9e892fab5f73dde566b9ffb73f2f0463d9a7 (diff) | |
Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/370
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b7ed..dc3addbe87 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; |