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authorSubrata Banik <subrata.banik@intel.com>2017-08-17 14:07:35 +0530
committerMartin Roth <martinroth@google.com>2017-08-21 16:29:55 +0000
commit7e9cb9281581fdf1b75ef5e6f32a1ec322e11c8f (patch)
tree920d7598a47db1ce343d54505d8bbc526c7d71b2
parentce4c9ec4f61cfba8a25adf74ad40d582859ea8b8 (diff)
soc/intel/skylake: Add support for all UART port index
Select LPSS UART Base address based on LPSS UART port index. Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/skylake/include/soc/iomap.h7
-rw-r--r--src/soc/intel/skylake/uart.c4
-rw-r--r--src/soc/intel/skylake/uart_debug.c2
3 files changed, 8 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index 52ef64041e..ff4e4b0396 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -23,8 +23,11 @@
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x4000000
-#define UART_DEBUG_BASE_ADDRESS 0xfe034000
-#define UART_DEBUG_BASE_SIZE 0x1000
+#define UART_DEBUG_BASE_0_SIZE 0x1000
+#define UART_BASE_0_ADDRESS 0xfe030000
+/* Both UART BAR 0 and 1 are 4KB in size */
+#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
+ UART_DEBUG_BASE_0_SIZE * (x)))
#define EARLY_I2C_BASE_ADDRESS 0xfe040000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 4e65859ea7..31389297b3 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -30,8 +30,8 @@ void pch_uart_read_resources(struct device *dev)
if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
/* Need to set the base and size for the resource allocator. */
- res->base = UART_DEBUG_BASE_ADDRESS;
- res->size = UART_DEBUG_BASE_SIZE;
+ res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
+ res->size = UART_DEBUG_BASE_0_SIZE;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
}
diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
index f3d576b3aa..eedf6564be 100644
--- a/src/soc/intel/skylake/uart_debug.c
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -22,5 +22,5 @@ uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2
* is currently only supported. */
- return UART_DEBUG_BASE_ADDRESS;
+ return UART_BASE_0_ADDR(idx);
}