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authorFurquan Shaikh <furquan@google.com>2020-05-11 16:35:08 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-13 00:16:58 +0000
commit6d28802d32c397650fadd556afe98da36e489473 (patch)
treef099d480eaaa4759147d71594bffcc0b05f179d4
parent3f3f53cd5e05eead7a8b8616244a4665bd14b22b (diff)
soc/amd/common/block/lpc: Add helper function lpc_early_init()
This change adds a helper function lpc_early_init() which does the following things: 1. Enables LPC controller 2. Disables any LPC decodes (These can be set up later by SoC or mainboard as required). 3. Sets SPI base so that MMIO base for SPI and eSPI controllers is initialized. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I016f29339466c3fee92fe9b62a13d72297c29b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/soc/amd/common/block/include/amdblocks/lpc.h9
-rw-r--r--src/soc/amd/common/block/lpc/lpc_util.c18
2 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 00210a7fe1..11acc78228 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -181,6 +181,15 @@ int lpc_set_wideio_range(uint16_t start, uint16_t size);
uintptr_t lpc_get_spibase(void);
/*
+ * Perform early initialization for LPC:
+ * 1. Enable LPC controller
+ * 2. Disable any LPC decodes
+ * 3. Set SPI Base which is the MMIO base for both SPI and eSPI controller (if supported by
+ * platform).
+ */
+void lpc_early_init(void);
+
+/*
* Sets MMIO base address for SPI controller and eSPI controller (if supported by platform).
*
* eSPI base = SPI base + 0x10000
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 2c47a8549a..d2a65c8c96 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -5,6 +5,7 @@
#include <device/device.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
+#include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>
#include <soc/iomap.h>
#include <soc/southbridge.h>
@@ -349,3 +350,20 @@ void lpc_enable_spi_rom(uint32_t enable)
pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
}
+
+static void lpc_enable_controller(void)
+{
+ u8 byte;
+
+ /* Enable LPC controller */
+ byte = pm_io_read8(PM_LPC_GATING);
+ byte |= PM_LPC_ENABLE;
+ pm_io_write8(PM_LPC_GATING, byte);
+}
+
+void lpc_early_init(void)
+{
+ lpc_enable_controller();
+ lpc_disable_decodes();
+ lpc_set_spibase(SPI_BASE_ADDRESS);
+}