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authorAaron Durbin <adurbin@chromium.org>2013-05-30 10:40:54 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-11-25 23:55:00 +0100
commit5afca1357fdaebc5c4ad2b2a963f3c239648ba76 (patch)
tree3669d93715af20c686ef30ba2796baa77ebe0ce2
parente9b50628d1c7f0cc8046903188562eebec8107bb (diff)
haswell: check for clean reset
When an INIT# is delivered to the CPU the CPU starts executing from the reset vector. However, the internal state is maintained. Therefore, check for such a condition and reset the system. Issues 'apreset warm' on the EC console. INIT# is sent and CPU notices it's not a clean reset and forces one. No hangs. Change-Id: I71229e0e5015ba8c60f5989c533268604ecc1ecc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57111 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/cpu/intel/haswell/bootblock.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index bb065c808d..e502cfa392 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -112,10 +112,28 @@ static void set_flex_ratio_to_tdp_nominal(void)
}
}
+static void check_for_clean_reset(void)
+{
+ msr_t msr;
+ msr = rdmsr(MTRRdefType_MSR);
+
+ /* Use the MTRR default type MSR as a proxy for detecting INIT#.
+ * Reset the system if any known bits are set in that MSR. That is
+ * an indication of the CPU not being properly reset. */
+ if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) {
+ outb(0x0, 0xcf9);
+ outb(0x6, 0xcf9);
+ while (1) {
+ asm("hlt");
+ }
+ }
+}
+
static void bootblock_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
+ check_for_clean_reset();
enable_rom_caching();
intel_update_microcode_from_cbfs();
}