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authorAamir Bohra <aamir.bohra@intel.com>2017-05-11 20:31:06 +0530
committerAaron Durbin <adurbin@chromium.org>2017-05-22 18:12:05 +0200
commit5196642870df642102699613642d412561f6609d (patch)
tree912f418f59c98c344205dda6716ebd6787f8f732
parent2d689f9e0d281b7ebe99340731511b51d9af21cc (diff)
soc/intel/skylake: Use Intel PCIe common code
Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/pcie.c112
3 files changed, 1 insertions, 113 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 2bfa61c2ef..e7cca3255a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPSS
+ select SOC_INTEL_COMMON_BLOCK_PCIE
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 6f1d1d5112..21f2f74811 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -66,7 +66,6 @@ ramstage-y += memmap.c
ramstage-y += monotonic_timer.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
ramstage-y += pch.c
-ramstage-y += pcie.c
ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c
deleted file mode 100644
index 9919d7abbb..0000000000
--- a/src/soc/intel/skylake/pcie.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <chip.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pciexp.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <soc/gpio.h>
-#include <soc/lpc.h>
-#include <soc/pch.h>
-#include <soc/pci_devs.h>
-#include <soc/cpu.h>
-#include <delay.h>
-
-static void pch_pcie_init(struct device *dev)
-{
- u16 reg16;
- u32 reg32;
-
- printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
-
- /* Enable SERR */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_SERR;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* Enable Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* Set Cache Line Size to 0x10 */
- pci_write_config8(dev, 0x0c, 0x10);
-
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
-
-#ifdef EVEN_MORE_DEBUG
- reg32 = pci_read_config32(dev, 0x20);
- printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x24);
- printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x28);
- printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x2c);
- printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
-#endif
-
- /* Clear errors in status registers */
- reg16 = pci_read_config16(dev, 0x06);
- pci_write_config16(dev, 0x06, reg16);
- reg16 = pci_read_config16(dev, 0x1e);
- pci_write_config16(dev, 0x1e, reg16);
-}
-
-static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
-{
- /* Set max snoop and non-snoop latency for the SOC */
- pci_write_config32(dev, off, 0x10031003);
-}
-
-static struct pci_operations pcie_ops = {
- .set_L1_ss_latency = pcie_set_L1_ss_max_latency,
-};
-
-static struct device_operations device_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pch_pcie_init,
- .enable = NULL,
- .scan_bus = pciexp_scan_bridge,
- .ops_pci = &pcie_ops,
-};
-
-static const unsigned short pcie_device_ids[] = {
- /* Sunrisepoint-LP */
- 0x9d10, 0x9d11, 0x9d12, 0x9d13, 0x9d14, 0x9d15, 0x9d16, 0x9d17,
- 0x9d18, 0x9d19, 0x9d1a, 0x9d1b,
- /* Sunrisepoint-H */
- 0xa290, 0xa291, 0xa292, 0xa293, 0xa294, 0xa295, 0xa296, 0xa297,
- 0xa298, 0xa299, 0xa29a, 0xa29b, 0xa29c, 0xa29d, 0xa29e, 0xa20f,
- 0xa110, 0xa111, 0xa112, 0xa113, 0xa114, 0xa115, 0xa116, 0xa117,
- 0xa118, 0xa119, 0xa11a, 0xa11b, 0xa11c, 0xa11d, 0xa11e, 0xa11f,
- 0xa167, 0xa168, 0xa169, 0xa16a,
- 0
-};
-
-static const struct pci_driver pch_pcie __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pcie_device_ids,
-};