diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-01-22 16:05:16 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-26 03:01:04 +0000 |
| commit | 4f65b87cf44f8351485621e1adbff916a70e008f (patch) | |
| tree | dec5b8174ea2fb796b3e94d450a6f0db0e9b2548 | |
| parent | 36eb5009943dd6c606d6eee5839b6407071c84b3 (diff) | |
soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
This patch updates SA DRAM registers bit definitions as per
SKL datasheet vol 2, doc 332688.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/skylake/acpi/systemagent.asl | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index 920062c021..e430b43ca9 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -32,26 +32,27 @@ Device (MCHC) Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */ Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 24, /* MCHBAR [38:15] */ Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + PXBR, 13, /* PCI Express BAR [38:26] */ Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */ Offset (0x70), /* ME Base Address */ MEBA, 64, + Offset (0xa0), TOM, 64, /* Top of Used Memory */ TUUD, 64, /* Top of Upper Used Memory */ |