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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-09-02 14:54:01 +0800
committerEdward O'Callaghan <quasisec@chromium.org>2020-09-02 23:32:59 +0000
commit456f8dc0a9786541ffb2f4c6baf2f02230870edc (patch)
tree26d19e0602439cc46ad71d8912c67d724bdd82e4
parentb56d596905bd09b090b07df7b01c3dfa21d2f6aa (diff)
mb/google/puff: Update DPTF parameters and TCC offset for faffy
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team. 3. Change PL2 min value from 25W to 15W. BUG=b:167477885 BRANCH=puff TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I68fdefe99cf36a39797c29ad84d08321bb8175f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
-rw-r--r--src/mainboard/google/hatch/variants/faffy/overridetree.cb22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index a5c8eff09b..a9e98d9f7e 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -1,4 +1,10 @@
chip soc/intel/cannonlake
+ register "tcc_offset" = "5" # TCC of 95C
+
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 15,
+ .tdp_pl2_override = 51,
+ }"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -276,16 +282,16 @@ chip soc/intel/cannonlake
device pci 04.0 on
chip drivers/intel/dptf
## Passive Policy
- register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)"
- register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 60, 5000)"
+ register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
+ register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 63, 5000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
- register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
+ register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
## Power Limits Control
# 10-15W PL1 in 200mW increments, avg over 28-32s interval
- # 25-51W PL2 in 1000mW increments, avg over 28-32s interval
+ # 15-51W PL2 in 1000mW increments, avg over 28-32s interval
register "controls.power_limits.pl1" = "{
.min_power = 10000,
.max_power = 15000,
@@ -293,18 +299,12 @@ chip soc/intel/cannonlake
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
- .min_power = 25000,
+ .min_power = 15000,
.max_power = 51000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,}"
- ## Charger Performance Control (Control, mA)
- register "controls.charger_perf[0]" = "{ 255, 1700 }"
- register "controls.charger_perf[1]" = "{ 24, 1500 }"
- register "controls.charger_perf[2]" = "{ 16, 1000 }"
- register "controls.charger_perf[3]" = "{ 8, 500 }"
-
device generic 0 on end
end
end # DPTF 0x1903