diff options
| author | Jens Rottmann <JRottmann@LiPPERTembedded.de> | 2013-02-19 15:01:06 +0100 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-06 19:07:28 +0100 |
| commit | 3914a316c3d3ab1ba45fe33394f37aaefdc62d61 (patch) | |
| tree | 2b8e8cc84bcd011a4fbda6574a99ae5206b45e33 | |
| parent | 069795a94716cdc5d5dbeed81d491004c3e6a58e (diff) | |
AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
The power up default for the 14M_25M_48M_OSC switchable clock output ball of
the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz,
which is the correct value for almost all SIOs. However, not for
'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
configurable for other clock speeds. A wrong SIO clock supply results in
funny RS232 output (wrong bit speed) and non-working PS/2.
We could switch back to 14 MHz in the mainboard's romstage.c, but then the
clock frequency would change twice. The resulting short 48 MHz burst causes
a handful of rubbish characters on RS232 on every boot until the SIO clock
has stabilized again.
This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
This does not affect any boards currently in the repository (yet).
Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/bootblock.c | 13 | ||||
| -rw-r--r-- | src/superio/Kconfig | 3 | ||||
| -rw-r--r-- | src/superio/smsc/Kconfig | 1 |
3 files changed, 14 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 8ed198a9e4..d21b4fdbfd 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,17 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl register to configure clock output on the + // 14M_25M_48M_OSC ball usually used for the Super-I/O. + // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, + // which is the SB800's power up default. We could switch back to 14 + // in the mainboard's romstage.c, but then the clock frequency would + // change twice. reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) +#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; } diff --git a/src/superio/Kconfig b/src/superio/Kconfig index 4e05a8ef35..32e60bb367 100644 --- a/src/superio/Kconfig +++ b/src/superio/Kconfig @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config SUPERIO_WANTS_14MHZ_CLOCK + bool + source src/superio/fintek/Kconfig source src/superio/intel/Kconfig source src/superio/ite/Kconfig diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index f863b3ed38..6aaa1127e9 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -44,6 +44,7 @@ config SUPERIO_SMSC_MEC1308 bool config SUPERIO_SMSC_SMSCSUPERIO bool + select SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_SIO1036 bool config SUPERIO_SMSC_SCH4037 |