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authorDuncan Laurie <dlaurie@chromium.org>2014-10-09 16:14:39 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-02 13:24:23 +0200
commit32dfd0625587015891d738794503b645ba9455ea (patch)
tree8fca463ffb8b94fae0e472a4d4331d59ad1e274b
parentafd6298c957651344686dacc9e6cb2cb1fd55bcd (diff)
broadwell: me: Fix typo and add missing phase state
Fix the typo of sate to state and add uKernel phase to just output the current state byte. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5f341ee6c58487aeb927cab0641742cb4071a6b7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de6149508c50d0770fedfbe352e9149abea87b4c Original-Change-Id: I520a4cc75faffa5feeb6113ffd7b07a48c4e6f28 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222677 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/soc/intel/broadwell/me_status.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c
index 4dfbeaec75..31eff3cd08 100644
--- a/src/soc/intel/broadwell/me_status.c
+++ b/src/soc/intel/broadwell/me_status.c
@@ -248,6 +248,10 @@ void intel_me_status(void)
me_progress_rom_values[hfs2->current_state]);
break;
+ case ME_HFS2_PHASE_UKERNEL: /* uKernel Phase */
+ printk(BIOS_DEBUG, "0x%02x", hfs2->current_state);
+ break;
+
case ME_HFS2_PHASE_BUP: /* Bringup Phase */
if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values)
&& me_progress_bup_values[hfs2->current_state])
@@ -274,7 +278,7 @@ void intel_me_status(void)
break;
default:
- printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x",
+ printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
hfs2->progress_code, hfs2->current_state);
}
printk(BIOS_DEBUG, "\n");