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| author | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-06 08:50:50 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-06 22:53:19 +0100 |
| commit | 31dc0acd9b8c3e5d30aa4e64ab1f24fac84bac1a (patch) | |
| tree | 5a4c40e8e751ebdc9bddaeb4e38a85f5e949457d | |
| parent | f4861df1e749885ec68ea0f17a3589aa6e79d13f (diff) | |
Google/Snow: enable sound hardware clocks
Set up the clocks used for sound and turn on the sound clock.
Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2587
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
| -rw-r--r-- | src/mainboard/google/snow/ramstage.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 5970357512..9f259ef30e 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/power.h> void hardwaremain(int boot_complete); void main(void) @@ -32,5 +34,14 @@ void main(void) ((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) - CONFIG_COREBOOT_TABLES_SIZE; + const unsigned epll_hz = 192000000; + const unsigned sample_rate = 48000; + const unsigned lr_frame_size = 256; + clock_epll_set_rate(epll_hz); + clock_select_i2s_clk_source(); + clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); + + power_enable_xclkout(); + hardwaremain(0); } |