diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 01:03:45 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-07 19:37:56 +0000 |
| commit | 2f8228d3c942638bc742cb076fb1204044424d64 (patch) | |
| tree | 5e859cf60cdfe2e188211a358055ba7508b2d9a2 | |
| parent | c715dc80f92f5cf1d29b53f2b2166e2a4f4b3dc4 (diff) | |
soc/amd/stoneyridge: remove STONEYRIDGE_ prefix of ACPI_IO_BASE define
Since I'm not sure if there are non-upstream boards that change the
default of the Kconfig value and the comment says that it needs to match
the binaryPI build, I'll do that change in a follow-up patch to allow
easy local reverts of that.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic0f08c6cb951994be6db19e10f73f0c621521c70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 20 |
2 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index ae2de671dd..af3bf1292a 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -59,7 +59,7 @@ unsigned long acpi_fill_madt(unsigned long current) */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 350618fc5c..92d99e4c36 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -27,16 +27,16 @@ /* I/O Ranges */ #define ACPI_SMI_CTL_PORT 0xb2 -#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ -#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ -#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ -#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ -#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */ +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ +#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ +#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x18) /* 4 bytes */ #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 |