diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-23 06:11:32 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-22 04:30:24 +0000 |
| commit | 23b081825daad678292036589d5e583547009ad1 (patch) | |
| tree | 4794e503af9473894d0389165335757ee909b3b6 | |
| parent | 548d350305324fb546ebe72b857a8fed0ee8589b (diff) | |
soc/intel/baytrail,broadwell: Refactor acpi_wake_source()
Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/baytrail/ramstage.c | 16 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/ramstage.c | 17 |
2 files changed, 11 insertions, 22 deletions
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index e199e9fc59..1e7cc089a0 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -117,12 +117,13 @@ static void fill_in_pattrs(void) } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(struct global_nvs *gnvs) +static void save_acpi_wake_source(void) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct global_nvs *gnvs = acpi_get_gnvs(); uint16_t pm1; - if (!ps) + if (!ps || !gnvs) return; pm1 = ps->pm1_sts & ps->pm1_en; @@ -142,14 +143,6 @@ static void s3_save_acpi_wake_source(struct global_nvs *gnvs) gnvs->pm1i); } -static void s3_resume_prepare(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - - if (gnvs && acpi_is_wakeup_s3()) - s3_save_acpi_wake_source(gnvs); -} - static void baytrail_enable_2x_refresh_rate(void) { u32 reg; @@ -172,7 +165,8 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); + if (acpi_is_wakeup_s3()) + save_acpi_wake_source(); /* Run reference code. */ baytrail_run_reference_code(); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index b4f38a5bfa..418e469828 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -12,13 +12,14 @@ #include <soc/intel/broadwell/chip.h> /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ -static void save_acpi_wake_source(struct global_nvs *gnvs) +static void save_acpi_wake_source(void) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + struct global_nvs *gnvs = acpi_get_gnvs(); uint16_t pm1; int gpe_reg; - if (!ps) + if (!ps || !gnvs) return; pm1 = ps->pm1_sts & ps->pm1_en; @@ -62,16 +63,10 @@ static void save_acpi_wake_source(struct global_nvs *gnvs) gnvs->pm1i, gnvs->gpei); } -static void s3_resume_prepare(void) -{ - struct global_nvs *gnvs = acpi_get_gnvs(); - - if (gnvs && acpi_is_wakeup_s3()) - save_acpi_wake_source(gnvs); -} - void broadwell_init_pre_device(void *chip_info) { - s3_resume_prepare(); + if (acpi_is_wakeup_s3()) + save_acpi_wake_source(); + broadwell_run_reference_code(); } |