AGESA: Trace execution with AGESA_EVENTLOG()

Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

39 files changed, 246 insertions, 299 deletions

diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c
index b9f5051617..72bcf42ad3 100644
--- a/src/cpu/amd/agesa/agesawrapper_s3.c
+++ b/src/cpu/amd/agesa/agesawrapper_s3.c
@@ -59,7 +59,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void)
 
 	status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
 
-	AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -93,7 +93,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
 			  (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
 
 	status = AmdS3LateRestore(AmdS3LateParamsPtr);
-	AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	return status;
@@ -122,7 +122,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
 	AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
 
 	status = AmdS3Save(AmdS3SaveParamsPtr);
-	AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	S3DataType = S3DataTypeNonVolatile;
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
index 26442f4913..53c27590db 100644
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ b/src/cpu/amd/agesa/amd_late_init.c
@@ -21,7 +21,6 @@
 #include <bootstate.h>
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #if CONFIG_AMD_SB_CIMX
 #include <sb_cimx.h>
@@ -32,7 +31,7 @@ static void agesawrapper_post_device(void *unused)
 	if (acpi_is_wakeup_s3())
 		return;
 
-	AGESAWRAPPER(amdinitlate);
+	agesawrapper_amdinitlate();
 
 #if CONFIG_AMD_SB_CIMX
 	sb_Late_Post();
@@ -40,7 +39,7 @@ static void agesawrapper_post_device(void *unused)
 	if (!acpi_s3_resume_allowed())
 		return;
 
-	AGESAWRAPPER(amdS3Save);
+	agesawrapper_amdS3Save();
 }
 
 BOOT_STATE_INIT_ENTRIES(agesa_bscb) = {
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index 3b13ee62ed..b1e9a61ec2 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -30,7 +30,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/sch4037/sch4037.h>
 #include <superio/smsc/sio1036/sio1036.h>
@@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x32);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x33);
@@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x36);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x37);
 	nb_Poweron_Init();
@@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 
 	post_code(0x43);
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index e0cf1d3b05..3a5c761530 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/kbc1100/kbc1100.h>
 #include "cpu/x86/lapic.h"
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index b1dcb5818a..abab68844a 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	outb(0xD2, 0xcd6);
 	outb(0x00, 0xcd7);
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -81,29 +80,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		val = inb(0xcd6);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x38);
 	printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
 
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		/* TODO: Disable cache is not ok. */
 		disable_cache_as_ram();
 	} else { /* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index fe84a90413..9a55e8060b 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -68,25 +67,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index fbe60fc911..5434ed3fe2 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f81865f/f81865f.h>
@@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index a64ba603e2..7dcd9b206c 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f81865f/f81865f.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 6a300d610d..193454542c 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -48,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u8 byte;
 	pci_devfn_t dev;
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	dev = PCI_DEV(0, 0x14, 3);
@@ -82,25 +81,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 682a76ea2c..f2bcccc519 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -29,7 +29,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/kbc1100/kbc1100.h>
 #include "cpu/x86/lapic.h"
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x35);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x36);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x38);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x39);
 	printk(BIOS_DEBUG, "sb_before_pci_init ");
@@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x43);
 	copy_and_run();
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index 7745338251..ac583dd33d 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include <sb_cimx.h>
@@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index f297da68df..c7c71a1e96 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -31,7 +31,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5572d/nct5572d.h>
@@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 
 	post_code(0x50);
 	copy_and_run();
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 24fa1944a3..3d1458bed1 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -31,7 +31,6 @@
 #include <console/loglevel.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
 #include "southbridge/amd/agesa/hudson/hudson.h"
@@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	//outb(0xD2, 0xcd6);
 	//outb(0x00, 0xcd7);
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -105,29 +104,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		val = inb(0xcd6);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x38);
 	printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
 
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		/* TODO: Disable cache is not ok. */
 		disable_cache_as_ram();
 	} else { /* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 57450ee3fa..fbc89a7fa2 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -19,7 +19,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -76,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	hudson_lpc_port80();
 #endif
 
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 
@@ -128,24 +127,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 95c7041b08..92b52929d5 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -33,7 +33,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <cpu/x86/cache.h>
 #include <sb_cimx.h>
@@ -88,29 +87,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index 449a8c1a59..9411ac87e2 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -18,7 +18,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -39,7 +38,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 30215ce907..534bdc44bf 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -19,7 +19,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -96,29 +95,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c
index 449a8c1a59..9411ac87e2 100644
--- a/src/mainboard/lenovo/g505s/romstage.c
+++ b/src/mainboard/lenovo/g505s/romstage.c
@@ -18,7 +18,6 @@
  */
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
@@ -39,7 +38,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	/* Set LPC decode enables. */
 	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
@@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 	post_code(0x39);
 
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
-		AGESAWRAPPER(amdinitpost);
+		agesawrapper_amdinitpost();
 		post_code(0x41);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 		disable_cache_as_ram();
 	} else {		/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
 		agesawrapper_amdinitcpuio();
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 02f4bc7c49..c4bf978553 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include "cpu/x86/lapic.h"
@@ -79,33 +78,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
 		/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
 		 * hang, looks like DRAM re-init goes wrong, don't know why. */
-		val = AGESAWRAPPER(amdinitpost);
+		val = agesawrapper_amdinitpost();
 		if (val == 7) /* fatal, amdinitenv below is going to hang */
 			outb(0x06, 0x0cf9); /* reset system harder instead */
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 2714d7f0e1..9d99894383 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -32,7 +32,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "cpu/x86/bist.h"
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
@@ -80,33 +79,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x35);
-	AGESAWRAPPER(amdinitmmio);
+	agesawrapper_amdinitmmio();
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed();
 	if (!s3resume) {
 		post_code(0x40);
 		/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
 		 * hang, looks like DRAM re-init goes wrong, don't know why. */
-		val = AGESAWRAPPER(amdinitpost);
+		val = agesawrapper_amdinitpost();
 		if (val == 7) /* fatal, amdinitenv below is going to hang */
 			outb(0x06, 0x0cf9); /* reset system harder instead */
 
 		post_code(0x42);
-		AGESAWRAPPER(amdinitenv);
+		agesawrapper_amdinitenv();
 
 	} else { 			/* S3 detect */
 		printk(BIOS_INFO, "S3 detected\n");
 
 		post_code(0x60);
-		AGESAWRAPPER(amdinitresume);
+		agesawrapper_amdinitresume();
 
-		AGESAWRAPPER(amds3laterestore);
+		agesawrapper_amds3laterestore();
 
 		post_code(0x61);
 		prepare_for_resume();
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index d584a4cd7c..9c48601f6a 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -28,7 +28,6 @@
 #include "cpu/x86/lapic.h"
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -46,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x30);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
@@ -66,7 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
@@ -81,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x3C);
 	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
@@ -101,10 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 	post_code(0x42);
 
 	post_code(0x50);
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index c67a9265af..2f4c828db5 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -28,7 +28,6 @@
 #include "cpu/x86/lapic.h"
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x30);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
@@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
@@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x3C);
 	nb_Ht_Init();
@@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 	post_code(0x42);
 
 	post_code(0x50);
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index a0e8bfd33d..8587ed1797 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -28,7 +28,6 @@
 #include "cpu/x86/lapic.h"
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "northbridge/amd/agesa/family10/reset_test.h"
 #include <nb_cimx.h>
 #include <sb_cimx.h>
@@ -44,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x30);
-	AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
+	agesawrapper_amdinitmmio();
 	post_code(0x31);
 
 	/* For serial port. */
@@ -69,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 
 	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
+	agesawrapper_amdinitreset();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x38);
@@ -84,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb_Poweron_Init();
 	}
 	post_code(0x3B);
-	AGESAWRAPPER(amdinitearly);
+	agesawrapper_amdinitearly();
 
 	post_code(0x3C);
 	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
@@ -104,10 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
+	agesawrapper_amdinitpost();
 
 	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	agesawrapper_amdinitenv();
 	post_code(0x42);
 
 	post_code(0x50);
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index e1eb69bf24..7b61b4cb49 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -23,7 +23,6 @@
 #include <stdint.h>
 #include "Porting.h"
 #include "AGESA.h"
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 /* Define AMD Ontario APPU SSID/SVID */
 #define AMD_APU_SVID		0x1022
@@ -48,7 +47,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void);
 AGESA_STATUS agesawrapper_amdinitpost(void);
 AGESA_STATUS agesawrapper_amdinitmid(void);
 
-AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus);
+void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func);
+#define AGESA_EVENTLOG(status, stdheader) \
+	agesawrapper_trace(status, stdheader, __func__)
 
 AGESA_STATUS agesawrapper_amdinitcpuio(void);
 AGESA_STATUS agesawrapper_amdinitmmio(void);
diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h
deleted file mode 100644
index 55742d4e8a..0000000000
--- a/src/northbridge/amd/agesa/agesawrapper_call.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _AGESAWRAPPER_CALL_H_
-#define _AGESAWRAPPER_CALL_H_
-
-#include <stdint.h>
-#include <console/console.h>
-#include "AGESA.h"
-
-/*
- * Possible AGESA_STATUS values:
- *
- * 0x0 = AGESA_SUCCESS
- * 0x1 = AGESA_UNSUPPORTED
- * 0x2 = AGESA_BOUNDS_CHK
- * 0x3 = AGESA_ALERT
- * 0x4 = AGESA_WARNING
- * 0x5 = AGESA_ERROR
- * 0x6 = AGESA_CRITICAL
- * 0x7 = AGESA_FATAL
- */
-static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
-{
-	const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
-					"AGESA_BOUNDS_CHK", "AGESA_ALERT",
-					"AGESA_WARNING", "AGESA_ERROR",
-					"AGESA_CRITICAL", "AGESA_FATAL"
-					};
-	if (sret > 7) return "unknown"; /* Non-AGESA error code */
-	return statusStrings[sret];
-}
-
-static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name)
-{
-	AGESA_STATUS ret;
-	printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name);
-	ret = func();
-	printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n",
-			name, decodeAGESA_STATUS(ret));
-	return (u32)ret;
-}
-
-#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func)
-
-#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func()
-
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14
-	/* TODO: These families do not pass valid HeapStatus. */
-#define AGESA_EVENTLOG(status) \
-	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0)
-#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x)
-#else
-#define AGESA_EVENTLOG(status, heapstatus) \
-	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus)
-#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y)
-#endif
-
-#endif
diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c
index 1deb343472..90640d9515 100644
--- a/src/northbridge/amd/agesa/eventlog.c
+++ b/src/northbridge/amd/agesa/eventlog.c
@@ -1,9 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
 
 #include <console/console.h>
+#include <stdint.h>
+#include <string.h>
 
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include "amdlib.h"
+#include "AGESA.h"
+#include "AMD.h"
+
+
+/*
+ * Possible AGESA_STATUS values:
+ *
+ * 0x0 = AGESA_SUCCESS
+ * 0x1 = AGESA_UNSUPPORTED
+ * 0x2 = AGESA_BOUNDS_CHK
+ * 0x3 = AGESA_ALERT
+ * 0x4 = AGESA_WARNING
+ * 0x5 = AGESA_ERROR
+ * 0x6 = AGESA_CRITICAL
+ * 0x7 = AGESA_FATAL
+ */
+static const char * decodeAGESA_STATUS(AGESA_STATUS sret)
+{
+	const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED",
+					"AGESA_BOUNDS_CHK", "AGESA_ALERT",
+					"AGESA_WARNING", "AGESA_ERROR",
+					"AGESA_CRITICAL", "AGESA_FATAL"
+					};
+	if (sret > 7) return "unknown"; /* Non-AGESA error code */
+	return statusStrings[sret];
+}
 
 #if 0
 
@@ -42,6 +86,7 @@ static void agesa_alert(EVENT_PARAMS *event)
 	switch (event->EventInfo) {
 		case MEM_ALERT_USER_TMG_MODE_OVERRULED:
 			printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x "
+
 					"TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n",
 					(unsigned int)event->DataParam1,
 					(unsigned int)event->DataParam2,
@@ -664,25 +709,19 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event)
 }
 #endif
 
-/**
- * @param  HeapStatus -the current HeapStatus
- */
-AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
+static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader)
 {
-	AGESA_STATUS Status;
 	EVENT_PARAMS AmdEventParams;
 
-	LibAmdMemFill(&AmdEventParams,
-			0,
-			sizeof(EVENT_PARAMS),
-			&(AmdEventParams.StdHeader));
+	memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS));
 
 	AmdEventParams.StdHeader.AltImageBasePtr = 0;
 	AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdEventParams.StdHeader.Func = 0;
 	AmdEventParams.StdHeader.ImageBasePtr = 0;
-	AmdEventParams.StdHeader.HeapStatus = HeapStatus;
-	Status = AmdReadEventLog(&AmdEventParams);
+	AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus;
+
+	AmdReadEventLog(&AmdEventParams);
 	while (AmdEventParams.EventClass != 0) {
 		printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",
 				(unsigned int)AmdEventParams.EventClass,
@@ -693,8 +732,14 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 		printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",
 				(unsigned int)AmdEventParams.DataParam3,
 				(unsigned int)AmdEventParams.DataParam4);
-		Status = AmdReadEventLog(&AmdEventParams);
+		AmdReadEventLog(&AmdEventParams);
 	}
+}
 
-	return Status;
+
+void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func)
+{
+	printk(BIOS_DEBUG, "%s() returned %s\n", func, decodeAGESA_STATUS(ret));
+	if (ret != AGESA_SUCCESS)
+		amd_readeventlog(StdHeader);
 }
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 1f615e5722..2c46129a84 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -832,7 +832,7 @@ static void amdfam10_domain_enable_resources(device_t dev)
 {
 	/* Must be called after PCI enumeration and resource allocation */
 	printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__);
-	AGESAWRAPPER(amdinitmid);
+	agesawrapper_amdinitmid();
 	printk(BIOS_DEBUG, "  ader - leaving %s.\n", __func__);
 }
 
diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c
index 9a39c0e64f..8d0fe909f1 100644
--- a/src/northbridge/amd/agesa/family12/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family12/agesawrapper.c
@@ -247,7 +247,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID)
 	AmdResetParams.HtConfig.Depth = 0;
 
 	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	return status;
 }
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID)
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
 	status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -296,7 +296,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID)
 
 	AmdCreateStruct(&AmdParamStruct);
 	status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	/* Initialize heap space */
@@ -321,7 +321,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 	AmdCreateStruct(&AmdParamStruct);
 	status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -370,7 +370,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID)
 	AmdCreateStruct(&AmdParamStruct);
 
 	status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -389,7 +389,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID)
 	AmdLateParams.StdHeader.ImageBasePtr = 0;
 
 	status = AmdInitLate(&AmdLateParams);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdLateParams.StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	DmiTable = AmdLateParams.DmiTable;
@@ -417,7 +417,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf
 	ApExeParams.StdHeader.ImageBasePtr = 0;
 
 	status = AmdLateRunApTask(&ApExeParams);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	return status;
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index bcebcd95a2..8d82925152 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -37,7 +37,6 @@
 
 #include "sb_cimx.h"
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 //#define FX_DEVS NODE_NUMS
 #define FX_DEVS 1
@@ -777,7 +776,7 @@ static void domain_enable_resources(device_t dev)
 	/* Enable MMIO on AMD CPU Address Map Controller */
 	agesawrapper_amdinitcpuio();
 
-	AGESAWRAPPER(amdinitmid);
+	agesawrapper_amdinitmid();
 	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
 }
 
diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c
index e1828306cb..8d80ef18e2 100644
--- a/src/northbridge/amd/agesa/family14/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family14/agesawrapper.c
@@ -157,7 +157,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID)
 	AmdResetParams.HtConfig.Depth = 0;
 
 	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	return status;
 }
@@ -182,7 +182,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID)
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
 	status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -204,7 +204,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID)
 
 	AmdCreateStruct(&AmdParamStruct);
 	status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	/* Initialize heap space */
@@ -229,8 +229,10 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 	AmdCreateStruct(&AmdParamStruct);
+
 	status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
+
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
 	 Modify D1F0x18
@@ -347,7 +349,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID)
 	AmdCreateStruct(&AmdParamStruct);
 
 	status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -375,7 +377,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID)
 	       (u32) AmdLateParamsPtr);
 
 	status = AmdInitLate(AmdLateParamsPtr);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	DmiTable = AmdLateParamsPtr->DmiTable;
@@ -414,7 +416,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
 	status = AmdLateRunApTask(&ApExeParams);
-	AGESA_EVENTLOG(status);
+	AGESA_EVENTLOG(status, &ApExeParams.StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	return status;
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index aec7157811..8d95dc4c79 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -36,7 +36,6 @@
 #include <cpu/amd/mtrr.h>
 
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #if CONFIG_AMD_SB_CIMX
 #include <sb_cimx.h>
 #endif
@@ -775,7 +774,7 @@ static void domain_enable_resources(device_t dev)
 		/* Enable MMIO on AMD CPU Address Map Controller */
 		agesawrapper_amdinitcpuio();
 
-		AGESAWRAPPER(amdinitmid);
+		agesawrapper_amdinitmid();
 	}
 
 	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c
index 4641881e9e..0552a02303 100644
--- a/src/northbridge/amd/agesa/family15/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family15/agesawrapper.c
@@ -210,7 +210,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
 #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
 	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
 #endif
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -243,7 +243,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
 	status = AmdInitEarly(AmdEarlyParamsPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 
 	GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices,
 				    &AmdParamStruct.StdHeader);
@@ -281,7 +281,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	OemCustomizeInitPost(PostParams);
 
 	status = AmdInitPost(PostParams);
-	AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &PostParams->StdHeader);
 
 	AmdReleaseStruct(&AmdParamStruct);
 
@@ -317,7 +317,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
 	}
 	EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitEnv(EnvParams);
-	AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &EnvParams->StdHeader);
 
 	AmdReleaseStruct(&AmdParamStruct);
 	return status;
@@ -369,7 +369,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
 		return status;
 	}
 	status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -396,7 +396,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 	printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr);
 
 	status = AmdInitLate(AmdLateParamsPtr);
-	AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdLateParamsPtr->StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	DmiTable = AmdLateParamsPtr->DmiTable;
@@ -438,7 +438,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf
 
 	printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data);
 	status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr);
-	AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdLateParams.StdHeader);
 	ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED));
 
 	return status;
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index de7d026a47..0700a5dc46 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -42,7 +42,6 @@
 #include <cpu/amd/amdfam15.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 #include "sb_cimx.h"
 
 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
@@ -710,7 +709,7 @@ static void domain_enable_resources(device_t dev)
 	/* Enable MMIO on AMD CPU Address Map Controller */
 	agesawrapper_amdinitcpuio();
 
-	AGESAWRAPPER(amdinitmid);
+	agesawrapper_amdinitmid();
 	printk(BIOS_DEBUG, "  Fam15 - leaving %s.\n", __func__);
 }
 
diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c
index 768541171b..043442af46 100644
--- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c
@@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
 	AmdResetParams.HtConfig.Depth = 0;
 
 	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	return status;
 }
@@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
 	status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	AmdCreateStruct(&AmdParamStruct);
 	PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitPost(PostParams);
-	AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &PostParams->StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	/* Initialize heap space */
 	EmptyHeap();
@@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
 	EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
 
 	status = AmdInitEnv(EnvParam);
-	AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &EnvParam->StdHeader);
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
 	 Modify D1F0x18
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
 
 	((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 	status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 	AmdCreateStruct(&AmdParamStruct);
 	AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitLate(AmdLateParams);
-	AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	DmiTable = AmdLateParams->DmiTable;
diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c
index c5924d2847..9d2fa9f95b 100644
--- a/src/northbridge/amd/agesa/family15rl/northbridge.c
+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c
@@ -43,7 +43,6 @@
 #include <cpu/amd/amdfam15.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
 
@@ -697,14 +696,14 @@ static void domain_read_resources(struct device *dev)
 static void domain_enable_resources(struct device *dev)
 {
 	if (acpi_is_wakeup_s3())
-		AGESAWRAPPER(fchs3laterestore);
+		agesawrapper_fchs3laterestore();
 
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!acpi_is_wakeup_s3()) {
 		/* Enable MMIO on AMD CPU Address Map Controller */
 		agesawrapper_amdinitcpuio();
 
-		AGESAWRAPPER(amdinitmid);
+		agesawrapper_amdinitmid();
 	}
 	printk(BIOS_DEBUG, "  ader - leaving %s.\n", __func__);
 }
diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c
index 768541171b..043442af46 100644
--- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c
@@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
 	AmdResetParams.HtConfig.Depth = 0;
 
 	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	return status;
 }
@@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
 	status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	AmdCreateStruct(&AmdParamStruct);
 	PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitPost(PostParams);
-	AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &PostParams->StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	/* Initialize heap space */
 	EmptyHeap();
@@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
 	EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
 
 	status = AmdInitEnv(EnvParam);
-	AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &EnvParam->StdHeader);
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
 	 Modify D1F0x18
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
 
 	((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 	status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 	AmdCreateStruct(&AmdParamStruct);
 	AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitLate(AmdLateParams);
-	AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	DmiTable = AmdLateParams->DmiTable;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 54a5c694eb..ac8d72af69 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -42,7 +42,6 @@
 #include <cpu/amd/amdfam15.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
 
@@ -695,14 +694,14 @@ static void domain_read_resources(device_t dev)
 static void domain_enable_resources(device_t dev)
 {
 	if (acpi_is_wakeup_s3())
-		AGESAWRAPPER(fchs3laterestore);
+		agesawrapper_fchs3laterestore();
 
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!acpi_is_wakeup_s3()) {
 		/* Enable MMIO on AMD CPU Address Map Controller */
 		agesawrapper_amdinitcpuio();
 
-		AGESAWRAPPER(amdinitmid);
+		agesawrapper_amdinitmid();
 	}
 	printk(BIOS_DEBUG, "  ader - leaving %s.\n", __func__);
 }
diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c
index 768541171b..043442af46 100644
--- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c
+++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c
@@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
 	AmdResetParams.HtConfig.Depth = 0;
 
 	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	return status;
 }
@@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
 	status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void)
 	AmdCreateStruct(&AmdParamStruct);
 	PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitPost(PostParams);
-	AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &PostParams->StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 	/* Initialize heap space */
 	EmptyHeap();
@@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
 	EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
 
 	status = AmdInitEnv(EnvParam);
-	AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &EnvParam->StdHeader);
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
 	 Modify D1F0x18
@@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
 
 	((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 	status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
 	AmdReleaseStruct(&AmdParamStruct);
 
 	return status;
@@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 	AmdCreateStruct(&AmdParamStruct);
 	AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 	status = AmdInitLate(AmdLateParams);
-	AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus);
+	AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
 	ASSERT(status == AGESA_SUCCESS);
 
 	DmiTable = AmdLateParams->DmiTable;
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 849f40cbd2..db12fc32e7 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -42,7 +42,6 @@
 #include <cpu/amd/amdfam16.h>
 #include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesawrapper_call.h>
 
 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
 
@@ -737,14 +736,14 @@ static void domain_read_resources(device_t dev)
 static void domain_enable_resources(device_t dev)
 {
 	if (acpi_is_wakeup_s3())
-		AGESAWRAPPER(fchs3laterestore);
+		agesawrapper_fchs3laterestore();
 
 	/* Must be called after PCI enumeration and resource allocation */
 	if (!acpi_is_wakeup_s3()) {
 		/* Enable MMIO on AMD CPU Address Map Controller */
 		agesawrapper_amdinitcpuio();
 
-		AGESAWRAPPER(amdinitmid);
+		agesawrapper_amdinitmid();
 	}
 	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
 }