soc/intel/xeon_sp: Use common cpu/intel romstage entry

This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.

Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

4 files changed, 24 insertions, 24 deletions

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index a83a3c3572..3d3e8037db 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -55,6 +55,7 @@ config	CPU_SPECIFIC_OPTIONS
 	select MICROCODE_BLOB_NOT_HOOKED_UP
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select FSP_CAR
+	select NO_SMM
 
 config MAINBOARD_USES_FSP2_0
 	  bool
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 07fe3debb4..a10075ab04 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -7,6 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
 
 bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
 romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
+romstage-y += ../../../cpu/intel/car/romstage.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c
 ramstage-y += memmap.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index 79ab47eaed..edc62cf881 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/smm.h>
 #include <soc/pci_devs.h>
@@ -20,3 +23,21 @@ void smm_region(uintptr_t *start, size_t *size)
 	*start = tseg_base;
 	*size = tseg_limit - tseg_base;
 }
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+	/*
+	 * We need to make sure ramstage will be run cached. At this
+	 * point exact location of ramstage in cbmem is not known.
+	 * Instruct postcar to cache 16 megs under cbmem top which is
+	 * a safe bet to cover ramstage.
+	 */
+	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+
+	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+	top_of_ram -= 16 * MiB;
+	postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK);
+	/* Cache the TSEG region */
+	if (CONFIG(TSEG_STAGE_CACHE))
+		postcar_enable_tseg_cache(pcf);
+}
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index f3e32fd9ca..2540c5c291 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <arch/romstage.h>
-#include <cbmem.h>
 #include <intelblocks/rtc.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
@@ -9,14 +8,8 @@
 #include <soc/romstage.h>
 #include <soc/util.h>
 
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
 {
-	struct postcar_frame pcf;
-	uintptr_t top_of_ram;
-
-	printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n");
-
-	console_init();
 	rtc_init();
 	if (soc_get_rtc_failed())
 		mainboard_rtc_failed();
@@ -26,23 +19,7 @@ asmlinkage void car_stage_entry(void)
 
 	unlock_pam_regions();
 
-	if (postcar_frame_init(&pcf, 1 * KiB))
-		die("Unable to initialize postcar frame.\n");
-
-	/*
-	 * We need to make sure ramstage will be run cached. At this point exact
-	 * location of ramstage in cbmem is not known. Instruct postcar to cache
-	 * 16 megs under cbmem top which is a safe bet to cover ramstage.
-	 */
-	top_of_ram = (uintptr_t)cbmem_top();
-	printk(BIOS_DEBUG, "top_of_ram: 0x%lx\n", top_of_ram);
-	postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB,
-		MTRR_TYPE_WRBACK);
-
-	/* Cache the memory-mapped boot media. */
-	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 	save_dimm_info();
-	run_postcar_phase(&pcf);
 }
 
 __weak void mainboard_memory_init_params(FSPM_UPD *mupd)