Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

27 files changed, 103 insertions, 57 deletions

diff --git a/src/Kconfig b/src/Kconfig
index 88df9ae8a8..bed6c7f8ee 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -385,9 +385,9 @@ config CBFS_SIZE
 	hex
 	default ROM_SIZE
 
-config CACHE_ROM_SIZE
+config CACHE_ROM_SIZE_OVERRIDE
 	hex
-	default CBFS_SIZE
+	default 0
 
 # TODO: Can probably be removed once all chipsets have kconfig options for it.
 config VIDEO_MB
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index fe1e29a5b3..fb653168b2 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -392,7 +392,7 @@ no_msr_11e:
 	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
 	/* Enable caching and Speculative Reads for Flash ROM device. */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
@@ -400,7 +400,7 @@ no_msr_11e:
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
 	rdmsr
-	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 #endif
 
diff --git a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
index a8d7cc54cb..61fb1c2636 100644
--- a/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
@@ -173,7 +173,7 @@ _clear_mtrrs_:
 	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
 	wrmsr
 
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
 	/* Enable Caching and speculative Reads for the
 	 * complete ROM now that we actually have RAM.
 	 */
@@ -182,7 +182,7 @@ _clear_mtrrs_:
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 #endif
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 35b51c5b59..edb2e80cdd 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -124,9 +124,9 @@ static void *setup_romstage_stack_after_car(void)
 
 	/* Cache the ROM as WP just below 4GiB. */
 	slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
-	slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
+	slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid);
 	slot = stack_push(slot, 0); /* upper base */
-	slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+	slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
 	num_mtrrs++;
 
 	/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index dce0e39dba..b791881d69 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -238,7 +238,7 @@ before_romstage:
 	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
 	wrmsr
 
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
 	/* Enable Caching and speculative Reads for the
 	 * complete ROM now that we actually have RAM.
 	 */
@@ -247,7 +247,7 @@ before_romstage:
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 #endif
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index b4119cc0b9..887d92bbe6 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -250,7 +250,7 @@ before_romstage:
 	movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
 	wrmsr
 
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
 	/* Enable Caching and speculative Reads for the
 	 * complete ROM now that we actually have RAM.
 	 */
@@ -259,7 +259,7 @@ before_romstage:
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 #endif
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index ac3c66b734..baf4ae8617 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -186,14 +186,14 @@ clear_mtrrs:
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 
-#if CONFIG_CACHE_ROM_SIZE
+#if CACHE_ROM_SIZE
 	/* Enable caching and Speculative Reads for Flash ROM device. */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
 #endif
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index d168978b54..dd404a887f 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -190,8 +190,8 @@ static struct memranges *get_physical_address_space(void)
 		 * when CONFIG_CACHE_ROM is enabled. The ROM is assumed
 		 * to be located at 4GiB - rom size. */
 		resource_t rom_base = RANGE_TO_PHYS_ADDR(
-			RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE));
-		memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE,
+			RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE));
+		memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE,
 		                 MTRR_TYPE_WRPROT);
 #endif
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 913ba47487..bbcde8a658 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -96,6 +96,13 @@ static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
 void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
 #endif
 
+/* Align up to next power of 2, suitable for ROMCC and assembler too.
+ * Range of result 256kB to 128MB is good enough here.
+ */
+#define _POW2_MASK(x)	((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \
+					(x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
+#define _ALIGN_UP_POW2(x)	((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
+
 #if !defined(CONFIG_RAMTOP)
 # error "CONFIG_RAMTOP not defined"
 #endif
@@ -104,11 +111,32 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif
 
-#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0)
-# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
+/* Select CACHE_ROM_SIZE to use with MTRR setup. For most cases this
+ * resolves to a suitable CONFIG_ROM_SIZE but some odd cases need to
+ * use CONFIG_CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig.
+ */
+#if (CONFIG_CACHE_ROM_SIZE_OVERRIDE != 0)
+# define CACHE_ROM_SIZE	CONFIG_CACHE_ROM_SIZE_OVERRIDE
+#else
+# if ((CONFIG_ROM_SIZE & (CONFIG_ROM_SIZE-1)) == 0)
+#  define CACHE_ROM_SIZE CONFIG_ROM_SIZE
+# else
+#  define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
+#  if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
+#   error "CACHE_ROM_SIZE is not optimal."
+#  endif
+# endif
+#endif
+
+#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0)
+# error "CACHE_ROM_SIZE is not a power of 2."
 #endif
 
-#define CACHE_ROM_BASE	(((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12)
+#define CACHE_ROM_BASE	(((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
+
+#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL)
+# error "CAR region (WB) and flash (WP) regions overlap."
+#endif
 
 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
 # error "CONFIG_RAMTOP must be a power of 2"
diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c
index 179822bebe..d61c5dc567 100644
--- a/src/mainboard/amd/dinar/agesawrapper.c
+++ b/src/mainboard/amd/dinar/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -271,9 +272,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+	MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 2e46516f90..718d2b2c2f 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -29,6 +29,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/kbc1100/kbc1100_early_init.c"
@@ -45,8 +46,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* all cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
 	 */
diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c
index ecd85ee497..a1cf7de64c 100644
--- a/src/mainboard/amd/olivehill/agesawrapper.c
+++ b/src/mainboard/amd/olivehill/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -166,9 +167,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c
index fcbddedca6..827ce6d4ec 100644
--- a/src/mainboard/amd/parmer/agesawrapper.c
+++ b/src/mainboard/amd/parmer/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -166,9 +167,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 58829b4b5e..98c64eda44 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -28,6 +28,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/fintek/f81865f/f81865f_early_serial.c"
@@ -58,8 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index af12026ff5..20c973c31f 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -29,6 +29,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/fintek/f81865f/f81865f_early_serial.c"
@@ -46,8 +47,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index 6331197437..c50f3a042b 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -166,9 +167,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c
index 8d068119fb..45b591a523 100644
--- a/src/mainboard/amd/torpedo/agesawrapper.c
+++ b/src/mainboard/amd/torpedo/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -279,9 +280,9 @@ agesawrapper_amdinitmmio (
   LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
 
   /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+  MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
   LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+  MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
   LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
   /* Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI */
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index e4cd21be1f..68687553f4 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -29,6 +29,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/lapic.h"
@@ -45,8 +46,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index b76e6a8e13..bf850a30c8 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -28,6 +28,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83627hf/early_serial.c"
@@ -49,8 +50,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr(0xc0010062, 0);
diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c
index 8300e34ae2..0f9212f9df 100644
--- a/src/mainboard/asrock/imb-a180/agesawrapper.c
+++ b/src/mainboard/asrock/imb-a180/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -166,9 +167,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c
index 529878b451..233d2bb57b 100644
--- a/src/mainboard/asus/f2a85-m/agesawrapper.c
+++ b/src/mainboard/asus/f2a85-m/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -166,9 +167,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index 05699cc4a5..705d42938d 100755
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -29,6 +29,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "drivers/pc80/i8254.c"
@@ -60,12 +61,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	msr.lo = ((0x0100000000ull - CONFIG_ROM_SIZE) | 5) & 0xFFFFFFFF;
-	msr.hi = ((0x0100000000ull - CONFIG_ROM_SIZE) | 5) >> 32;
+	msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF;
+	msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32;
 	wrmsr (MSR_MTRR_VARIABLE_BASE6, msr);
 
-	msr.lo = ((0x1000000000ull - CONFIG_ROM_SIZE) | 0x800) & 0xFFFFFFFF;
-	msr.hi = ((0x1000000000ull - CONFIG_ROM_SIZE) | 0x800) >> 32;
+	msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF;
+	msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32;
 	wrmsr (MSR_MTRR_VARIABLE_MASK6, msr);
 
 	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 093a047557..9ecd0872bc 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -28,6 +28,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/early_serial.c"
@@ -58,8 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 88b81001c0..4f62268e0e 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -28,6 +28,7 @@
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83627dhg/w83627dhg.h"
@@ -58,8 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 * All cores: allow caching of flash chip code and data
 	 * (there are no cache-as-ram reliability concerns with family 14h)
 	 */
-	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+	__writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800);
 
 	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 31995753e7..4704c26eab 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -192,9 +193,9 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+	MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c
index 49abe2517b..7700489104 100644
--- a/src/mainboard/supermicro/h8scm/agesawrapper.c
+++ b/src/mainboard/supermicro/h8scm/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -192,9 +193,9 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+	MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c
index 7fba1b7c2f..e5419db953 100644
--- a/src/mainboard/tyan/s8226/agesawrapper.c
+++ b/src/mainboard/tyan/s8226/agesawrapper.c
@@ -24,6 +24,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <cpu/x86/mtrr.h>
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "cpuRegisters.h"
@@ -202,9 +203,9 @@ agesawrapper_amdinitmmio (
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
+	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
 	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;