diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 17:47:06 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:36 +0000 |
| commit | 08143576466918413bfae2303abc4d0d16ae5b5c (patch) | |
| tree | e142830967562c879cc81b388b2c6e63d8d7366f | |
| parent | 93d9517795b58fca2639bc66e359a61219e82b81 (diff) | |
nb/intel/ironlake: Add QPI Link register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 10 |
2 files changed, 10 insertions, 5 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index bd42f21006..aa2399f136 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -65,6 +65,11 @@ */ #define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) +#define QPI_QPILCP 0x40 /* QPI Link Capability */ +#define QPI_QPILCL 0x48 /* QPI Link Control */ +#define QPI_QPILS 0x50 /* QPI Link Status */ +#define QPI_DEF_RMT_VN_CREDITS 0x58 /* Default Available Remote Credits */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 2c475694d4..f955a1ea46 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3950,11 +3950,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8_OR(0x2ca8, 1); // guess } - pci_read_config32(QPI_LINK_0, 0x048); // !!!! - pci_write_config32(QPI_LINK_0, 0x048, 0x140000); - pci_read_config32(QPI_LINK_0, 0x058); // !!!! - pci_write_config32(QPI_LINK_0, 0x058, 0x64555); - pci_read_config32(QPI_LINK_0, 0x058); // !!!! + pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!! + pci_write_config32(QPI_LINK_0, QPI_QPILCL, 0x140000); + pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! + pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); + pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); gav(MCHBAR32(0x1af0)); // !!!! |