diff options
| author | Martin Roth <martinroth@google.com> | 2017-12-09 10:39:38 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-11 17:31:38 +0000 |
| commit | fbfe654c06f947b61633c519458ed63f6c3904b7 (patch) | |
| tree | 876074edd47ede974558628ee9742a1ee4dd78d4 | |
| parent | 1533dfdd0e85cd2390e33e8eb96379d567b19136 (diff) | |
commonlib: Add timestamp codes for AGESA
BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.
Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/commonlib/include/commonlib/timestamp_serialized.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 6c8d9552b5..088212a82e 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -77,6 +77,22 @@ enum timestamp_id { TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, + /* 900-920 reserved for vendorcode extensions (900-940: AMD AGESA) */ + TS_AGESA_INIT_RESET_START = 900, + TS_AGESA_INIT_RESET_DONE = 901, + TS_AGESA_INIT_EARLY_START = 902, + TS_AGESA_INIT_EARLY_DONE = 903, + TS_AGESA_INIT_POST_START = 904, + TS_AGESA_INIT_POST_DONE = 905, + TS_AGESA_INIT_ENV_START = 906, + TS_AGESA_INIT_ENV_DONE = 907, + TS_AGESA_INIT_MID_START = 908, + TS_AGESA_INIT_MID_DONE = 909, + TS_AGESA_INIT_LATE_START = 910, + TS_AGESA_INIT_LATE_DONE = 911, + TS_AGESA_INIT_RTB_START = 912, + TS_AGESA_INIT_RTB_DONE = 913, + /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ TS_ME_INFORM_DRAM_WAIT = 940, TS_ME_INFORM_DRAM_DONE = 941, @@ -181,6 +197,22 @@ static const struct timestamp_id_to_name { { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, { TS_START_KERNEL, "jumping to kernel" }, + /* AMD AGESA related timestamps */ + { TS_AGESA_INIT_RESET_START, "calling AmdInitReset" }, + { TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" }, + { TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" }, + { TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" }, + { TS_AGESA_INIT_POST_START, "calling AmdInitPost" }, + { TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" }, + { TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" }, + { TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" }, + { TS_AGESA_INIT_MID_START, "calling AmdInitMid" }, + { TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" }, + { TS_AGESA_INIT_LATE_START, "calling AmdInitLate" }, + { TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" }, + { TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" }, + { TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" }, + /* Intel ME related timestamps */ { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, |