diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-02 22:35:28 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-03 00:12:52 +0100 |
| commit | f94698c34ba96f336b22d3905597eb7d61c2bcdb (patch) | |
| tree | 17099d578e244b45865bd7e9e96dad4f00f37c65 | |
| parent | 41f55b734f3eb96450c415e37e9cb1500c509e6d (diff) | |
Revert "gigabyte/ga-b75m-d3h: Add new Intel mainboard"
Breaks abuild and is dependent on WIP, is WIP itself.
This reverts commit d7d0c8134854cba72f0c3fe25946b27ce0364b43.
Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7319
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
22 files changed, 0 insertions, 1699 deletions
diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index c46b979ead..ff96a17687 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,8 +27,6 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" -config BOARD_GIGABYTE_GA_B75M_D3H - bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -43,7 +41,6 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" -source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig deleted file mode 100644 index 85e9ec2d82..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ /dev/null @@ -1,75 +0,0 @@ -if BOARD_GIGABYTE_GA_B75M_D3H - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select ARCH_X86 - select CPU_INTEL_SOCKET_LGA1155 - select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE - select SOUTHBRIDGE_INTEL_C216 - select SUPERIO_ITE_IT8728F - select BOARD_ROMSIZE_KB_8192 - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select HAVE_ACPI_RESUME - select HAVE_SMI_HANDLER - select INTEL_INT15 - select VGA - select INTEL_EDID - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG - select IVYBRIDGE_LVDS - select UDELAY_TSC - select EARLY_CBMEM_INIT - -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 - -config USBDEBUG_HCD_INDEX - int - default 2 - -config MAINBOARD_DIR - string - default gigabyte/ga-b75m-d3h - -config MAINBOARD_PART_NUMBER - string - default "GA-B75M-D3H" - -config IRQ_SLOT_COUNT - int - default 18 - -config MAX_CPUS - int - default 8 - -# No need to override the chipset VGA_BIOS_ID. -config VGA_BIOS_FILE - string - default "pci8086,0162.rom" - -config HAVE_IFD_BIN - bool - default n - -config HAVE_ME_BIN - bool - default n - -config IFD_BIOS_SECTION - string - default "0x00600000:0x007fffff" - -config IFD_ME_SECTION - string - default "0x00001000:0x004fffff" - -# UNCOMMENT BELOW WHEN YOU BUILD WITH REAL ME IMAGE -#config IFD_GBE_SECTION -# string -# default "0x00fff000:0x00000fff" - -endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc deleted file mode 100644 index a2efaddcef..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c -romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl deleted file mode 100644 index f87af3c192..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl +++ /dev/null @@ -1 +0,0 @@ -// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl deleted file mode 100644 index 09cff9aa64..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -Scope (\_SB) -{ - Device (PWRB) - { - Name (_HID, EisaId("PNP0C0C")) - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl deleted file mode 100644 index 1448aeb027..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} - -/* The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ - -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} - diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl deleted file mode 100644 index 753fc29dcc..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse - diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl deleted file mode 100644 index f71611afcd..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -// Thermal Zone - -Scope (\_TZ) -{ - ThermalZone (THRM) - { - Name (_TC1, 0x02) - Name (_TC2, 0x03) - - // Thermal zone polling frequency: 10 seconds - Name (_TZP, 100) - - // Thermal sampling period for passive cooling: 10 seconds - Name (_TSP, 100) - - // Convert from Degrees C to 1/10 Kelvin for ACPI - Method (CTOK, 1) - { - // 10th of Degrees C - Multiply (Arg0, 10, Local0) - - // Convert to Kelvin - Add (Local0, 2732, Local0) - - Return (Local0) - } - - // Threshold for OS to shutdown - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - // Threshold for passive cooling - Method (_PSV, 0, Serialized) - { - Return (CTOK (\TPSV)) - } - - // Processors used for passive cooling - Method (_PSL, 0, Serialized) - { - Return (\PPKG ()) - } - } -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl deleted file mode 100644 index f87af3c192..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl +++ /dev/null @@ -1 +0,0 @@ -// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c deleted file mode 100644 index 73b1c11f84..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <arch/acpigen.h> -#include <arch/smp/mpspec.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> - -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - memset((void *)gnvs, 0, sizeof(*gnvs)); - gnvs->apic = 1; - gnvs->mpen = 1; /* Enable Multi Processing */ - gnvs->pcnt = dev_count_cpu(); - - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - - // the lid is open by default. - gnvs->lids = 1; - - acpi_update_thermal_table(gnvs); -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt deleted file mode 100644 index 312f6ef947..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default deleted file mode 100644 index 21d75e5ece..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default +++ /dev/null @@ -1,9 +0,0 @@ -boot_option=Fallback -last_boot=Fallback -baud_rate=115200 -debug_level=Spew -power_on_after_fail=Enable -nmi=Enable -volume=0x3 -sata_mode=AHCI -hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout deleted file mode 100644 index 7c8af49755..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout +++ /dev/null @@ -1,152 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -400 8 h 0 volume - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -#411 10 r 0 unused -421 1 e 9 sata_mode -#422 2 r 0 unused - -# coreboot config options: cpu -424 1 e 2 hyper_threading -#425 7 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 549 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M - -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb deleted file mode 100644 index bd9cdf6f1c..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ /dev/null @@ -1,87 +0,0 @@ -chip northbridge/intel/sandybridge - - # Enable DVI Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - device cpu_cluster 0 on - chip cpu/intel/socket_LGA1155 - device lapic 0 on end - end - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end - end - - device domain 0 on - subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller - - chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - - # GPI routing - register "alt_gp_smi_en" = "0x0000" - - # Set max SATA speed to 6.0 Gb/s - register "sata_port_map" = "0x3f" - register "sata_interface_speed_support" = "0x3" - register "gen1_dec" = "0x003c0a01" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - device pci 14.0 off end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge (ethernet here) - device pci 1f.0 on # ISA/LPC bridge - chip superio/ite/it8728f - device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0xa30 - io 0x62 = 0xa20 - irq 0x70 = 9 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x0 - io 0x62 = 0xa00 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.a off end # IR - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # SATA Controller 2 - device pci 1f.6 on end # Thermal - end - end -end - diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl deleted file mode 100644 index 320996356d..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - #include "acpi/mainboard.asl" - - // global NVS and variables - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - #include "acpi/thermal.asl" - - #include <cpu/intel/model_206ax/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - } - } - - /* Chipset specific sleep states */ - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c deleted file mode 100644 index 9b93c9a190..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c +++ /dev/null @@ -1,283 +0,0 @@ -#include "southbridge/intel/bd82x6x/gpio.h" -static const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /*1GPIO0 */ - .gpio1 = GPIO_MODE_GPIO, /*0SIO_EXT_SMI# */ - .gpio2 = GPIO_MODE_GPIO, /*1NOT USED */ - .gpio3 = GPIO_MODE_GPIO, /*1NOT USED */ - .gpio4 = GPIO_MODE_GPIO, /*1NOT USED */ - .gpio5 = GPIO_MODE_GPIO, /*0INTH# */ - .gpio6 = GPIO_MODE_GPIO, /*0SIO_EXT_SCI# */ - .gpio7 = GPIO_MODE_GPIO, /*1GE_SCR_WP# */ - .gpio8 = GPIO_MODE_GPIO, /*0NOT USED */ - .gpio9 = GPIO_MODE_NATIVE, /*1USB_OC5# */ - .gpio10 = GPIO_MODE_NATIVE, /*1USB_OC6# */ - .gpio11 = GPIO_MODE_NATIVE, /*0SMBALERT# */ - .gpio12 = GPIO_MODE_GPIO, /*1GPIO12 */ - .gpio13 = GPIO_MODE_GPIO, /*0GPIO13 */ - .gpio14 = GPIO_MODE_NATIVE, /*1USB_OC7# */ - .gpio15 = GPIO_MODE_GPIO, /*1GPIO15 */ - .gpio16 = GPIO_MODE_GPIO, /*1WWAN_LED_ON */ - .gpio17 = GPIO_MODE_GPIO, /*0WLAN_LED_ON */ - .gpio18 = GPIO_MODE_NATIVE, /*1PCIE_CLKREQ_WLAN# */ - .gpio19 = GPIO_MODE_GPIO, /*1BBS_BIT0 */ - .gpio20 = GPIO_MODE_NATIVE, /*0PCIE_CLKREQ_CARD# */ - .gpio21 = GPIO_MODE_GPIO, /*0BT_DET# / TP29 */ - .gpio22 = GPIO_MODE_GPIO, /*0MODEL_ID0 */ - .gpio23 = GPIO_MODE_NATIVE, /*1LCD_BK_OFF */ - .gpio24 = GPIO_MODE_GPIO, /*1GPIO24 */ - .gpio25 = GPIO_MODE_NATIVE, /*1PCIE_REQ_WWAN# / TP89 */ - .gpio26 = GPIO_MODE_NATIVE, /*1CLK_PCIE_REQ4# / TP59 */ - .gpio27 = GPIO_MODE_GPIO, /*1MSATA_DTCT# */ - .gpio28 = GPIO_MODE_GPIO, /*1PLL_ODVR_EN */ - .gpio29 = GPIO_MODE_GPIO, /*1WLAN_AOAC_ON */ - .gpio30 = GPIO_MODE_NATIVE, /*1SUS_PWR_ACK */ - .gpio31 = GPIO_MODE_GPIO, /*1AC_PRESENT */ -}; - -static const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio1 = GPIO_DIR_INPUT, - .gpio2 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio4 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio6 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_OUTPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_OUTPUT, - .gpio13 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_OUTPUT, - .gpio16 = GPIO_DIR_INPUT, - .gpio17 = GPIO_DIR_INPUT, - .gpio18 = GPIO_DIR_INPUT, - .gpio19 = GPIO_DIR_INPUT, - .gpio20 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio22 = GPIO_DIR_INPUT, - .gpio23 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, - .gpio25 = GPIO_DIR_INPUT, - .gpio26 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, - .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_INPUT, - .gpio30 = GPIO_DIR_OUTPUT, - .gpio31 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_level = { - .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_HIGH, - .gpio3 = GPIO_LEVEL_HIGH, - .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, - .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_HIGH, - .gpio9 = GPIO_LEVEL_HIGH, - .gpio10 = GPIO_LEVEL_HIGH, - .gpio11 = GPIO_LEVEL_HIGH, - .gpio12 = GPIO_LEVEL_HIGH, - .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_LOW, - .gpio18 = GPIO_LEVEL_LOW, - .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, - .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, - .gpio25 = GPIO_LEVEL_LOW, - .gpio26 = GPIO_LEVEL_LOW, - .gpio27 = GPIO_LEVEL_HIGH, - .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, - .gpio31 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_invert = { - .gpio13 = GPIO_INVERT, -}; - -static const struct pch_gpio_set1 pch_gpio_set1_blink = { - .gpio18 = GPIO_BLINK, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio32 = GPIO_MODE_GPIO, /* PCI_CLKRUN# */ - .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */ - .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */ - .gpio35 = GPIO_MODE_GPIO, /* BT_ON */ - .gpio36 = GPIO_MODE_GPIO, /* NOT USED */ - .gpio37 = GPIO_MODE_GPIO, /* NOT USED */ - .gpio38 = GPIO_MODE_GPIO, /* NOT USED */ - .gpio39 = GPIO_MODE_GPIO, /* NOT USED */ - .gpio40 = GPIO_MODE_NATIVE, /* USB_OC1# */ - .gpio41 = GPIO_MODE_NATIVE, /* USB_OC2# */ - .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */ - .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */ - .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */ - .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */ - .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */ - .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */ - .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */ - .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */ - .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */ - .gpio51 = GPIO_MODE_NATIVE, /* BBS_BIT1 */ - .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */ - .gpio53 = GPIO_MODE_NATIVE, /* PWM_SELECT# / TP44 */ - .gpio54 = GPIO_MODE_NATIVE, /* PCI_REQ3# */ - .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */ - .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */ - .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */ - .gpio59 = GPIO_MODE_NATIVE, /* USB_OC0_1# */ - .gpio60 = GPIO_MODE_NATIVE, /* DRAMRST_CNTRL_PCH */ - .gpio61 = GPIO_MODE_NATIVE, /* LPCPD# */ - .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */ - .gpio63 = GPIO_MODE_NATIVE, /* TP51 */ -}; - -static const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio32 = GPIO_DIR_OUTPUT, - .gpio33 = GPIO_DIR_OUTPUT, - .gpio34 = GPIO_DIR_INPUT, - .gpio35 = GPIO_DIR_OUTPUT, - .gpio36 = GPIO_DIR_INPUT, - .gpio37 = GPIO_DIR_INPUT, - .gpio38 = GPIO_DIR_INPUT, - .gpio39 = GPIO_DIR_INPUT, - .gpio40 = GPIO_DIR_INPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio44 = GPIO_DIR_INPUT, - .gpio45 = GPIO_DIR_INPUT, - .gpio46 = GPIO_DIR_INPUT, - .gpio47 = GPIO_DIR_INPUT, - .gpio48 = GPIO_DIR_INPUT, - .gpio49 = GPIO_DIR_INPUT, - .gpio50 = GPIO_DIR_INPUT, - .gpio51 = GPIO_DIR_OUTPUT, - .gpio52 = GPIO_DIR_INPUT, - .gpio53 = GPIO_DIR_OUTPUT, - .gpio54 = GPIO_DIR_INPUT, - .gpio55 = GPIO_DIR_OUTPUT, - .gpio56 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, - .gpio58 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio59 = GPIO_DIR_INPUT, - .gpio61 = GPIO_DIR_OUTPUT, - .gpio62 = GPIO_DIR_OUTPUT, - .gpio63 = GPIO_DIR_OUTPUT, -}; - -static const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, - .gpio34 = GPIO_LEVEL_HIGH, - .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, - .gpio37 = GPIO_LEVEL_LOW, - .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_HIGH, - .gpio40 = GPIO_LEVEL_HIGH, - .gpio41 = GPIO_LEVEL_HIGH, - .gpio42 = GPIO_LEVEL_HIGH, - .gpio43 = GPIO_LEVEL_HIGH, - .gpio44 = GPIO_LEVEL_HIGH, - .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, - .gpio47 = GPIO_LEVEL_LOW, - .gpio48 = GPIO_LEVEL_HIGH, - .gpio49 = GPIO_LEVEL_HIGH, - .gpio50 = GPIO_LEVEL_HIGH, - .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, - .gpio53 = GPIO_LEVEL_HIGH, - .gpio54 = GPIO_LEVEL_HIGH, - .gpio55 = GPIO_LEVEL_HIGH, - .gpio56 = GPIO_LEVEL_LOW, - .gpio57 = GPIO_LEVEL_HIGH, - .gpio58 = GPIO_LEVEL_HIGH, - .gpio59 = GPIO_LEVEL_HIGH, - .gpio60 = GPIO_LEVEL_HIGH, - .gpio61 = GPIO_LEVEL_HIGH, - .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_HIGH, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_NATIVE, /* CLK_FLEX0 / TP38 */ - .gpio65 = GPIO_MODE_NATIVE, /* CLK_FLEX1 / TP45 */ - .gpio66 = GPIO_MODE_NATIVE, /* CLK_FLEX2 / TP83 */ - .gpio67 = GPIO_MODE_NATIVE, /* CLK_FLEX3 / TP82 */ - .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */ - .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */ - .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */ - .gpio71 = GPIO_MODE_NATIVE, /* WWAN_OFF# */ - .gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW# */ - .gpio73 = GPIO_MODE_GPIO, /* PCIECLKRQ0# / TP39 */ - .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */ - .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */ -}; - -static const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_OUTPUT, - .gpio65 = GPIO_DIR_OUTPUT, - .gpio66 = GPIO_DIR_OUTPUT, - .gpio67 = GPIO_DIR_OUTPUT, - .gpio68 = GPIO_DIR_INPUT, - .gpio69 = GPIO_DIR_INPUT, - .gpio70 = GPIO_DIR_INPUT, - .gpio71 = GPIO_DIR_INPUT, - .gpio72 = GPIO_DIR_INPUT, - .gpio73 = GPIO_DIR_INPUT, - .gpio74 = GPIO_DIR_INPUT, - .gpio75 = GPIO_DIR_INPUT, -}; - -static const struct pch_gpio_set3 pch_gpio_set3_level = { - .gpio64 = GPIO_LEVEL_HIGH, - .gpio65 = GPIO_LEVEL_HIGH, - .gpio66 = GPIO_LEVEL_HIGH, - .gpio67 = GPIO_LEVEL_HIGH, - .gpio68 = GPIO_LEVEL_HIGH, - .gpio69 = GPIO_LEVEL_LOW, - .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, - .gpio72 = GPIO_LEVEL_HIGH, - .gpio73 = GPIO_LEVEL_LOW, - .gpio74 = GPIO_LEVEL_HIGH, - .gpio75 = GPIO_LEVEL_HIGH, -}; - -const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, - .set3 = { - .mode = &pch_gpio_set3_mode, - .direction = &pch_gpio_set3_direction, - .level = &pch_gpio_set3_level, - }, -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c deleted file mode 100644 index 29f8a4522b..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Vendor Name : IDT - * Vendor ID : 0x10ec0269 - * Subsystem ID : 0x17aa21fa - * Revision ID : 0x100303 - */ - - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC - 0x17aa21fa, // Subsystem ID - 0x0000007d, // Number of 4 dword sets - -/* Bits 31:28 - Codec Address */ -/* Bits 27:20 - NID */ -/* Bits 19:8 - Verb ID */ -/* Bits 7:0 - Payload */ - -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21FA), - -/* NID 0x0A - External Microphone Connector - * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020), - -/* NID 0x0B - Headphone Connector - * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F), - -/* NID 0x0C - Not connected - * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0), - -/* NID 0x0D - Internal Speakers - * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110), - -/* NID 0x0F - Not connected - * Config=0x40F000F0 - */ - AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0), - -/* NID 0x11 - Internal Microphone - * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) - */ - AZALIA_PIN_CFG(0x0, 0x11, 0xD5A30140), - AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140), - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830), - AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0), - - 0x01970804, - 0x01870803, - 0x01470740, - 0x00970600, - - 0x00370600, - 0x00270600, - 0x00270600, - 0x00270600, - - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0), - AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205), - AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0), - - /* - * Hardware EQ Parameters - * Sample Rate 88200 - */ - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, - 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, - 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, - 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, - 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, - 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, - 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, - 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, - 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, - 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, - 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, - 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, - 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, - 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, - 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, - 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, - 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, - 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, - 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, - 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, - 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, - 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, - 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, - 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, - 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, - 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, - 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, - 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, - 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, - 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, - 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, - 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, - 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, - 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, - 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, - 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, - 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, - 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, - 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, - 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, - 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, - 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, - 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, - 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, - 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, - 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, - 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, - 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, - 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, - - /* - * Hardware EQ Parameters - * Sample Rate 96000 - */ - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, - 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, - 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, - 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, - 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, - 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, - 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, - 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, - 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, - 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, - 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, - 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, - 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, - 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, - 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, - 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, - 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, - 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, - 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, - 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, - 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, - 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, - 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, - 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, - 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, - 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, - 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, - 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, - 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, - 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, - 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, - 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, - 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, - 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, - 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, - 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, - 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, - 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, - 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, - 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, - 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, - 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, - 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, - 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, - 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, - 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, - 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, - 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, - 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, - 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, - 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, - - /* SAFEDSP Parameters */ - 0x022782C1, 0x02277127, 0x02277227, 0x02278801, - 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, - 0x02278B0F, 0x0017B008, - - /* Misc entries */ - 0x00B707C0, /* Enable PortB as Output with HP amp */ - 0x00D70740, /* Enable PortD as Output */ - 0x0017A200, /* Disable ClkEn of PortSenseTst */ - 0x0017C621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ - 0x0017A208, /* Enable ClkEn of PortSenseTst */ - 0x00170500, /* Set power state to D0 */ - - /* --- Next Codec --- */ - -/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 - */ - /* coreboot specific header */ - 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI - 0x80860101, // Subsystem ID - 0x00000004, // Number of IDs - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ - AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) -}; - -const u32 pc_beep_verbs[] = { - 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ -}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c deleted file mode 100644 index 045d6993ba..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <drivers/intel/gma/int15.h> -#include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <smbios.h> -#include <device/pci.h> -#include <cbfs.h> -#include <pc80/keyboard.h> -#include <ec/lenovo/h8/h8.h> -#include <build.h> - -void mainboard_suspend_resume(void) -{ - /* Call SMM finalize() handlers before resume */ - outb(0xcb, 0xb2); -} - -const char *smbios_mainboard_bios_version(void) -{ - /* Satisfy thinkpad_acpi. */ - if (strlen(CONFIG_LOCALVERSION)) - return "CBET4000 " CONFIG_LOCALVERSION; - else - return "CBET4000 " COREBOOT_VERSION; -} - - - -static void mainboard_init(device_t dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x38c0) = 0x00000007; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; - - pc_keyboard_init(); -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c deleted file mode 100644 index 9f8a29fa7d..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <pc80/mc146818rtc.h> -#include <delay.h> -#include <southbridge/intel/bd82x6x/nvs.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/bd82x6x/me.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <cpu/intel/model_206ax/model_206ax.h> - -/* The southbridge SMI handler checks whether gnvs has a - * valid pointer before calling the trap handler - */ -extern global_nvs_t *gnvs; - -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - -} - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 data) -{ - u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; - - printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, - data); - - if (!pmbase) - return 0; - - switch (data) { - case APM_CNT_ACPI_ENABLE: - break; - case APM_CNT_ACPI_DISABLE: - break; - case APM_CNT_FINALIZE: - printk(BIOS_DEBUG, "APMC: FINALIZE\n"); - if (mainboard_finalized) { - printk(BIOS_DEBUG, "APMC#: Already finalized\n"); - return 0; - } - - intel_me_finalize_smm(); - intel_pch_finalize_smm(); - intel_sandybridge_finalize_smm(); - intel_model_206ax_finalize_smm(); - - mainboard_finalized = 1; - break; - - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - -} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h b/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h deleted file mode 100644 index f8b9141c50..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/onboard.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef GAB75MD3H_ONBOARD_H -#define GAB75MD3H_ONBOARD_H - -#include <arch/smp/mpspec.h> - -#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c deleted file mode 100644 index 3ba6319932..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define SUPERIO_BASE 0x2e -#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) -#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) -#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) - -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <arch/acpi.h> -#include <console/console.h> -#include <superio/ite/it8728f/it8728f.h> -#include <superio/ite/common/ite.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" -#include <arch/cpu.h> -#include <cpu/x86/msr.h> - -static void it8728f_b75md3h_disable_reboot(device_t dev) -{ - /* GPIO SIO settings */ - ite_reg_write(dev, 0xEF, 0x7E); // magic - - ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 - ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 - ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port - ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 - ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! - ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! - ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in - ite_reg_write(dev, 0xe9, 0x27); // bus select disable - ite_reg_write(dev, 0xf0, 0x10); // ? - ite_reg_write(dev, 0xf1, 0x42); // ? - ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) - - /* EC SIO settings */ - ite_reg_write(IT8728F_EC, 0xf1, 0xc0); - ite_reg_write(IT8728F_EC, 0xf6, 0xf0); - ite_reg_write(IT8728F_EC, 0xf9, 0x48); - ite_reg_write(IT8728F_EC, 0x60, 0x0a); - ite_reg_write(IT8728F_EC, 0x61, 0x30); - ite_reg_write(IT8728F_EC, 0x62, 0x0a); - ite_reg_write(IT8728F_EC, 0x63, 0x20); - ite_reg_write(IT8728F_EC, 0x30, 0x01); -} - -void rcba_config(void) -{ -/* - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); - - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); - - RCBA32(0x3500) = 0x2000035f; - RCBA32(0x3504) = 0x2000035f; - RCBA32(0x3508) = 0x2000035f; - RCBA32(0x350c) = 0x2000035f; - RCBA32(0x3510) = 0x2000035f; - RCBA32(0x3514) = 0x2000035f; - RCBA32(0x3518) = 0x2000035f; - RCBA32(0x351c) = 0x2000035f; - RCBA32(0x3520) = 0x2000035f; - RCBA32(0x3524) = 0x2000035f; - RCBA32(0x3528) = 0x2000035f; - RCBA32(0x352c) = 0x2000035f; - RCBA32(0x3530) = 0x2000035f; - RCBA32(0x3534) = 0x2000035f; - RCBA32(0x3560) = 0x024c8001; - RCBA32(0x3564) = 0x000024a3; - RCBA32(0x3568) = 0x00040002; - RCBA32(0x356c) = 0x01000050; - RCBA32(0x3570) = 0x02000662; - RCBA32(0x3574) = 0x18000f9f; - RCBA32(0x3578) = 0x1800ff4f; - RCBA32(0x357c) = 0x0001d530; - RCBA32(0x35a0) = 0xc0300c03; - RCBA32(0x35a4) = 0x00241803; - - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); - - outw (0x0000, DEFAULT_PMBASE | 0x003c); - - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; -// RCBA32(0x3418) = 0x1fee1fe1; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -*/ - /* Disable unused devices (board specific) */ - RCBA32(FD) = 0x17ee1fe1; -} - -void pch_enable_lpc(void) -{ - /* - * Enable: - * EC Decode Range PortA30/A20 - * SuperIO Port2E/2F - * PS/2 Keyboard/Mouse Port60/64 - * FDD Port3F0h-3F5h and Port3F7h - */ - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | - CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); - - /* Initialize SuperIO */ - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, -// { 1, 5, 4 }, -// { 1, 5, 4 }, -// { 1, 5, 6 }, -// { 1, 5, 5 }, -// { 1, 5, 5 }, -// { 1, 5, 6 }, -}; - -void mainboard_get_spd(spd_raw_data *spd) { - read_spd (&spd[0], 0x50); - read_spd (&spd[1], 0x51); - read_spd (&spd[2], 0x52); - read_spd (&spd[3], 0x53); -} - -#if 0 -static void dmi_config(void) -{ - DMIBAR32(0x0218) = 0x06aa0b0c; - DMIBAR32(0x021c) = 0x0b0d0b0d; - DMIBAR32(0x0300) = 0x0011028d; - DMIBAR32(0x0304) = 0x002102cd; - DMIBAR32(0x030c) = 0x007d004b; - DMIBAR32(0x0310) = 0x007e004c; - DMIBAR32(0x0318) = 0x002304ad; - DMIBAR32(0x031c) = 0x003304ed; - DMIBAR32(0x03b8) = 0x005c05a4; - DMIBAR32(0x03bc) = 0x006c05e4; - DMIBAR32(0x0530) = 0x41d3b000; - DMIBAR32(0x0534) = 0x00019f80; - DMIBAR32(0x0ba4) = 0x0000000d; - DMIBAR32(0x0d80) = 0x1c9cfc0b; - DMIBAR32(0x0e1c) = 0x20000000; - DMIBAR32(0x0e2c) = 0x20000000; -} -#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h deleted file mode 100644 index ed08c8a2d1..0000000000 --- a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef GAB75MD3H_THERMAL_H -#define GAB75MD3H_THERMAL_H - - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 - - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 - -#endif |