diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-01-21 21:05:54 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-26 22:40:53 +0000 |
| commit | e98722856e37c31152f1561891a1428a7bdbb557 (patch) | |
| tree | 30bd6574ccadbf31d0ff801f663288d6d99b3683 | |
| parent | 92b487dd4b842b5bb614d4e525b0f32bde1d8ca1 (diff) | |
soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and report
Both early platform information reporting in bootblock and common code
CPU driver will add support for cannonlake D0 stepping processor.
BUG=None
TEST=Boot up system with D0 stepping CPU installed, check serial log
that can display as D0 stepping.
Change-Id: I76ee974ee027100d7853a110f95b1601987492e4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 969a8f73f9..c81e53435c 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -35,6 +35,7 @@ static struct { { CPUID_CANNONLAKE_A0, "Cannonlake A0" }, { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, + { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, }; static struct { diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e19127c1b3..ebd55b5188 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -63,6 +63,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_CANNONLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0 }, + { X86_VENDOR_INTEL, CPUID_CANNONLAKE_D0 }, { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, |