diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-07-30 18:56:52 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-26 00:27:54 +0100 |
| commit | e8ab775c811365fe984d90489ed605e6a17f2f19 (patch) | |
| tree | 6cca867de9c05837d4ebc8ade7755c97b5ff4b4b | |
| parent | eb5e5882596d52963f1e897dcfc5829958517152 (diff) | |
arm64: Seed the stack at stage_entry
Seed the stack in order to avoid boot process from complaining false stack
overflow.
BUG=chrome-os-partner:30824
BRANCH=None
TEST=Compiles successfully for rush and stack overflow error fixed in boot flow
Change-Id: I5d29d24eb5270d38a35a32171881b1aab8bf32e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 26e53568e82ad8418c20c2410f0cbc5c444c9917
Original-Change-Id: Ie51e1bcd263e3b886feb2e0e9c7d544f23c3444e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210594
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8942
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/arch/arm64/stage_entry.S | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 0f49c40e2d..c18c9cfeaa 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -20,6 +20,29 @@ #include <arch/asm.h> +ENTRY(seed_stack) + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr x0, .stack_bottom + ldr x1, .stack_top + ldr x2, =0xdeadbeefdeadbeef + ldr x3, =0x8 + +init_stack_loop: + str x2, [x0] + add x0, x0, x3 + cmp x0, x1 + bne init_stack_loop + +load_stack: + b arm64_init + .align 4 + .stack_bottom: + .quad _stack +ENDPROC(seed_stack) + ENTRY(arm64_el3_startup) /* Set all bits in SCTLR_EL3 to 0 except RES1 and RES0 */ mrs x0, SCTLR_EL3 @@ -37,7 +60,7 @@ ENTRY(arm64_el3_startup) isb /* Load up the stack if non-zero. */ - ldr x0, .stack + ldr x0, .stack_top cmp x0, #0 b.eq 1f mov sp, x0 @@ -58,10 +81,10 @@ ENTRY(arm64_el3_startup) * to the Kconfig option for cpu0. However, this code can be relocated * and reused to start up secondary cpus. */ - .stack: + .stack_top: .quad _estack .entry: - .quad arm64_init + .quad seed_stack ENDPROC(arm64_el3_startup) .global arm64_el3_startup_end arm64_el3_startup_end: |