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authorShankar, Vaibhav <vaibhav.shankar@intel.com>2016-07-18 12:07:34 -0700
committerAaron Durbin <adurbin@chromium.org>2016-08-02 18:40:15 +0200
commitd5817c887e2d0719fedaf89303bf72d04bf6be0f (patch)
treec4b6864ccbc50ef48a3b496f239b24f74b37e64d
parent67d169721ade4e4d9ca827a4817894522696b5de (diff)
intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/15777 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/intel/amenia/gpio.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h
index a3b76117be..4a4d08feff 100644
--- a/src/mainboard/intel/amenia/gpio.h
+++ b/src/mainboard/intel/amenia/gpio.h
@@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */
PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */
- PAD_CFG_NF(PMU_SLP_S0_B, NONE, DEEP, NF1), /* PMU_SLP_S0_N */
+ PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */
PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
@@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(PMC_SPI_CLK, DN_20K), /* PMC_SPI_CLK */
/* PMIC */
PAD_NC(PMIC_PWRGOOD, NONE), /* PMIC_PWRGOOD */
- PAD_NC(PMIC_RESET_B, NONE), /* PMIC_RESET_B */
+ PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */
PAD_NC(GPIO_213, NONE), /* PMIC_SDWN_B */
PAD_NC(GPIO_214, DN_20K), /* PMIC_BCUDISW2 */
PAD_NC(GPIO_215, DN_20K), /* PMIC_BCUDISCRIT */