soc/intel/apl: drop LPC pad configuration code

Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.

Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 10 insertions, 49 deletions

diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md
index 13aeed5bd2..d4e8ca7df4 100644
--- a/Documentation/getting_started/gpio.md
+++ b/Documentation/getting_started/gpio.md
@@ -129,3 +129,13 @@ If no pullup or pulldown is declared with these, they may end up "floating",
 i.e., not at logical high or logical low. This can cause problems such as
 unwanted power consumption or not reading the pin correctly, if it was intended
 to be strapped.
+
+## Pad-related known issues and workarounds
+
+### LPC_CLKRUNB blocks S0ix states when board uses eSPI
+
+When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode.
+Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up
+enable/disable etc are ignored. Leaving this pin in native mode will keep the
+LPC Controller awake and prevent S0ix entry. This issues is know at least on
+Apollolake and Geminilake.
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index e37ab2070f..4a5f40f42a 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -3,57 +3,10 @@
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/rtc.h>
-#include <soc/gpio.h>
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include "chip.h"
 
-static const struct pad_config lpc_gpios[] = {
-#if CONFIG(SOC_INTEL_GEMINILAKE)
-#if !CONFIG(SOC_ESPI)
-	PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_CLKOUT0 */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_CLKOUT1 */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_AD0 */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_AD1 */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_AD2 */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_AD3 */
-	PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPC_FRAMEB */
-#else
-	/*
-	 * LPC_CLKRUNB should be in GPIO mode for eSPI. Other pin settings
-	 * i.e. Rx path enable/disable, Tx path enable/disable, pull up
-	 * enable/disable etc are ignored. Leaving this pin in Native mode
-	 * will keep LPC Controller awake and prevent S0ix entry
-	 */
-	PAD_NC(GPIO_154, NONE),
-#endif /* !CONFIG(SOC_ESPI) */
-#else
-	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
-#endif
-};
-
-void lpc_configure_pads(void)
-{
-	gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
-}
-
 void lpc_soc_init(struct device *dev)
 {
 	const struct soc_intel_apollolake_config *cfg;
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 98318aced5..fc5ce8e357 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -65,8 +65,6 @@ each soc will need to define the init. */
 void lpc_soc_init(struct device *dev);
 /* Fill up LPC IO resource structure inside SoC directory */
 void pch_lpc_soc_fill_io_resources(struct device *dev);
-/* Init LPC GPIO pads */
-void lpc_configure_pads(void);
 /* Set LPC BIOS Control BILD bit. */
 void lpc_set_bios_interface_lock_down(void);
 /* Set LPC BIOS Control LE bit. */