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authorAaron Durbin <adurbin@chromium.org>2014-08-01 16:50:27 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-03-25 22:31:28 +0100
commitd25ead2589c47ae476975cb6c42354c3a12fb3f9 (patch)
tree99f08fb783800efae7cc9af6403479e9d2994df7
parente06771c74ebf3b307b6b8690c9c68233bbee14ac (diff)
tegra132: introduce romstage_mainboard_init()
Instead of calling out with function names all the possible combinations of interface and device provide one call to the mainboard to configure all the necessary bits. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and ran on rush. Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210838 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8901 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
-rw-r--r--src/mainboard/google/rush/romstage.c9
-rw-r--r--src/mainboard/google/rush_ryu/romstage.c15
-rw-r--r--src/soc/nvidia/tegra132/include/soc/romstage.h6
-rw-r--r--src/soc/nvidia/tegra132/romstage.c32
4 files changed, 42 insertions, 20 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index 8edcba8d6a..b4d9714699 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -34,7 +34,7 @@ static void configure_tpm_i2c_bus(void)
i2c_init(2);
}
-void mainboard_init_tpm_i2c(void)
+static void mainboard_init_tpm_i2c(void)
{
clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
@@ -51,7 +51,7 @@ void mainboard_init_tpm_i2c(void)
configure_tpm_i2c_bus();
}
-void mainboard_init_ec_spi(void)
+static void mainboard_init_ec_spi(void)
{
clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
@@ -75,9 +75,10 @@ void mainboard_init_ec_spi(void)
clock_configure_source(sbc1, CLK_M, 500);
}
-void mainboard_init_ec_i2c(void)
+void romstage_mainboard_init(void)
{
- /* Empty - Rush uses SPI to communicate with the EC */
+ mainboard_init_tpm_i2c();
+ mainboard_init_ec_spi();
}
void mainboard_configure_pmc(void)
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 1c08718543..4ebb8edf24 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -38,7 +38,7 @@ static void configure_ec_i2c_bus(void)
i2c_init(1);
}
-void mainboard_init_tpm_i2c(void)
+static void mainboard_init_tpm_i2c(void)
{
clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
@@ -54,12 +54,7 @@ void mainboard_init_tpm_i2c(void)
configure_tpm_i2c_bus();
}
-void mainboard_init_ec_spi(void)
-{
- /* Empty - Ryu uses I2C to communicate with the EC */
-}
-
-void mainboard_init_ec_i2c(void)
+static void mainboard_init_ec_i2c(void)
{
clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0);
@@ -73,6 +68,12 @@ void mainboard_init_ec_i2c(void)
configure_ec_i2c_bus();
}
+void romstage_mainboard_init(void)
+{
+ mainboard_init_tpm_i2c();
+ mainboard_init_ec_i2c();
+}
+
void mainboard_configure_pmc(void)
{
}
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h
index dcf6ad6079..14358d8d58 100644
--- a/src/soc/nvidia/tegra132/include/soc/romstage.h
+++ b/src/soc/nvidia/tegra132/include/soc/romstage.h
@@ -20,10 +20,10 @@
#ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
#define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
+void romstage(void);
+void romstage_mainboard_init(void);
+
void mainboard_configure_pmc(void);
void mainboard_enable_vdd_cpu(void);
-void mainboard_init_tpm_i2c(void);
-void mainboard_init_ec_spi(void);
-void mainboard_init_ec_i2c(void);
#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
index be431f7975..8d12dedaf1 100644
--- a/src/soc/nvidia/tegra132/romstage.c
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -32,7 +32,25 @@
#include <soc/clock.h>
#include <soc/romstage.h>
-void romstage(void);
+void __attribute__((weak)) romstage_mainboard_init(void)
+{
+ /* Default empty implementation. */
+}
+
+static void *load_ramstage(void)
+{
+ void *entry;
+ /*
+ * This platform does not need to cache a loaded ramstage nor do we
+ * go down this path on resume. Therefore, no romstage_handoff is
+ * required.
+ */
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
+ CONFIG_CBFS_PREFIX "/ramstage");
+
+ return entry;
+}
+
void romstage(void)
{
void *entry;
@@ -67,12 +85,14 @@ void romstage(void)
ccplex_load_mts();
printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
- mainboard_init_tpm_i2c();
- mainboard_init_ec_spi();
- mainboard_init_ec_i2c();
+ romstage_mainboard_init();
- entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
- CONFIG_CBFS_PREFIX "/ramstage");
+ entry = load_ramstage();
+
+ if (entry == NULL) {
+ printk(BIOS_INFO, "T132 romstage: error loading ramstage\n");
+ clock_halt_avp();
+ }
cbmemc_reinit();