diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-28 20:48:17 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-07 16:52:31 +0100 |
| commit | c764c7488b2cb536bc4e09e6a8a639beeabfddeb (patch) | |
| tree | 8f63f9a4386a83ac1f5269f005c1e4394a94c75a | |
| parent | 046d2174207d79681fe98206ce92074ac610957e (diff) | |
cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure
When microcode updates are enabled, this fixes an issue identical
to that described in GIT hash 7b22d84d:
* drivers/pc80: Add optional spinlock for nvram CBFS access
Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12063
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/Kconfig | 4 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/smp/spinlock.h | 7 | ||||
| -rw-r--r-- | src/cpu/amd/microcode/microcode.c | 19 |
3 files changed, 28 insertions, 2 deletions
diff --git a/src/Kconfig b/src/Kconfig index a8b086913a..f6702eadaf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -489,6 +489,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK SR565x, that cannot handle concurrent CBFS accesses from multiple APs during early startup. +config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK + bool + default n + config HAVE_MONOTONIC_TIMER def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 057d9e3f8f..39a81d289c 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,10 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) +#if !defined(__PRE_RAM__) \ + || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ + || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ + || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -16,6 +19,8 @@ spinlock_t *romstage_console_lock(void); void initialize_romstage_console_lock(void); spinlock_t* romstage_nvram_cbfs_lock(void); void initialize_romstage_nvram_cbfs_lock(void); +spinlock_t* romstage_microcode_cbfs_lock(void); +void initialize_romstage_microcode_cbfs_lock(void); #endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 37d395a560..314d07013b 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -20,6 +20,7 @@ #include <cpu/amd/microcode.h> #include <cbfs.h> #include <arch/io.h> +#include <smp/spinlock.h> #define UCODE_DEBUG(fmt, args...) \ do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0) @@ -197,14 +198,30 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) return; } +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + spin_lock(romstage_microcode_cbfs_lock()); +#endif +#endif + ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { UCODE_DEBUG("microcode file not found. Skipping updates.\n"); - +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + spin_unlock(romstage_microcode_cbfs_lock()); +#endif +#endif return; } amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); + +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + spin_unlock(romstage_microcode_cbfs_lock()); +#endif +#endif } } |