soc/intel/tigerlake: Move tco_configure to bootblock

On ChromeOS systems with a serial-enabled BIOS and vboot writing a new
firmware image to the Chrome EC, it was possible for the TCO watchdog
timer to trip 2 times before tco_configure() was called in romstage.
This caused an extra reboot of the system (at a rather inopportune time)
and because the EC didn't perform a full reset, the system boots into
recovery mode.

This patch moves the call to tco_configure() for Tiger Lake from
romstage to bootblock, in order to make sure the TCO watchdog timer is
halted before vboot_sync_ec() runs in romstage. It should be harmless to
configure the TCO device earlier in the boot flow.

BUG=b:160272400
TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 4 insertions, 4 deletions

diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c
index 54ad85a82e..e7d97c50bf 100644
--- a/src/soc/intel/tigerlake/bootblock/bootblock.c
+++ b/src/soc/intel/tigerlake/bootblock/bootblock.c
@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <intelblocks/systemagent.h>
+#include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
 #include <soc/bootblock.h>
 
@@ -25,4 +26,7 @@ void bootblock_soc_init(void)
 {
 	report_platform_info();
 	pch_init();
+
+	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
 }
diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c
index e800ce50bd..9fd8a1e43e 100644
--- a/src/soc/intel/tigerlake/romstage/pch.c
+++ b/src/soc/intel/tigerlake/romstage/pch.c
@@ -1,14 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
 #include <soc/romstage.h>
 
 void pch_init(void)
 {
-	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
-	tco_configure();
-
 	/* Program SMBUS_BASE_ADDRESS and Enable it */
 	smbus_common_init();
 }