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authorGreg Watson <jarrah@users.sourceforge.net>2004-01-14 17:21:22 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-01-14 17:21:22 +0000
commitb020d53352c1bbe1084c9c499b45cfb345fc8677 (patch)
tree1938b5ec4d8a2e388a19b0a9b38e7497da16b9b4
parentbf5b58480129dcd6a770f3f2b237511fb295918e (diff)
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/cpu/ppc/ppc4xx/cache.S22
-rw-r--r--src/cpu/ppc/ppc4xx/ppc4xx.inc10
-rw-r--r--src/cpu/ppc/ppc4xx/sdram.c64
-rw-r--r--src/mainboard/embeddedplanet/ep405pc/init.c4
-rw-r--r--src/mainboard/motorola/sandpoint/Config.lb12
-rw-r--r--targets/embeddedplanet/ep405pc/Config.lb6
6 files changed, 68 insertions, 50 deletions
diff --git a/src/cpu/ppc/ppc4xx/cache.S b/src/cpu/ppc/ppc4xx/cache.S
index 44282da7eb..1104112d64 100644
--- a/src/cpu/ppc/ppc4xx/cache.S
+++ b/src/cpu/ppc/ppc4xx/cache.S
@@ -55,9 +55,9 @@ invalidate_icache:
.globl invalidate_dcache
invalidate_dcache:
- addi r6,0,0x0000 /* clear GPR 6 */
+ li r6,0x0000 /* clear GPR 6 */
/* Do loop for # of dcache congruence classes. */
- addi r7,r0, (DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
+ li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
1:
@@ -68,21 +68,21 @@ invalidate_dcache:
.globl flush_dcache
flush_dcache:
- addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
+ lis r9,0x0002 /* set mask for EE and CE msr bits */
ori r9,r9,0x8000
mfmsr r12 /* save msr */
andc r9,r12,r9
mtmsr r9 /* disable EE and CE */
- addi r10,r0,0x0001 /* enable data cache for unused memory */
+ li r10,0x0001 /* enable data cache for unused memory */
mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
or r10,r10,r9 /* bit 31 in dccr */
mtdccr r10
/* do loop for # of congruence classes. */
- addi r10,r0,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
- addi r11,r0,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
+ li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2)
+ li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */
mtctr r10
- addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
+ li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */
add r11,r10,r11 /* add to get to other side of cache line */
1:
lwz r3,0(r10) /* least recently used side */
@@ -102,13 +102,13 @@ icache_enable:
bl invalidate_icache
mtlr r8
isync
- addis r3,r0, 0x8000 /* set bit 0 */
+ lis r3,0x8000 /* set bit 0 */
mticcr r3
blr
.globl icache_disable
icache_disable:
- addis r3,r0, 0x0000 /* clear bit 0 */
+ lis r3,0x0000 /* clear bit 0 */
mticcr r3
isync
blr
@@ -125,7 +125,7 @@ dcache_enable:
bl invalidate_dcache
mtlr r8
isync
- addis r3,r0, 0x8000 /* set bit 0 */
+ lis r3,0x8000 /* set bit 0 */
mtdccr r3
blr
@@ -134,7 +134,7 @@ dcache_disable:
mflr r8
bl flush_dcache
mtlr r8
- addis r3,r0, 0x0000 /* clear bit 0 */
+ lis r3,0x0000 /* clear bit 0 */
mtdccr r3
blr
diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc
index bbd8949a62..eea497734e 100644
--- a/src/cpu/ppc/ppc4xx/ppc4xx.inc
+++ b/src/cpu/ppc/ppc4xx/ppc4xx.inc
@@ -66,7 +66,7 @@
mtevpr r4 /* clear Exception Vector Prefix Reg */
li r4,0x1000 /* set ME bit (Machine Exceptions) */
oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
-// mtmsr r4 /* change MSR */
+ mtmsr r4 /* change MSR */
li r4,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */
/* the dbsr is cleared by setting */
/* bits to 1) */
@@ -97,6 +97,8 @@
* Enable dcache region containing DCACHE_RAM_BASE
* On reset all regions are set to write-back, so we
* just leave them alone.
+ *
+ * dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27))
*/
lis r4, DCACHE_RAM_BASE@ha
@@ -107,9 +109,3 @@
slw r4, r0, r4
mtdccr r4 /* data cache enable */
sync
-
- /* DMA Status, clear to come up clean */
-
- addis r3,r0, 0xFFFF /* Clear all existing DMA status */
- ori r3,r3, 0xFFFF
- mtdcr dmasr, r3
diff --git a/src/cpu/ppc/ppc4xx/sdram.c b/src/cpu/ppc/ppc4xx/sdram.c
index 5de2ab029c..6d7ed1a08b 100644
--- a/src/cpu/ppc/ppc4xx/sdram.c
+++ b/src/cpu/ppc/ppc4xx/sdram.c
@@ -26,20 +26,49 @@
#include <ppc4xx.h>
#include <timer.h>
#include <clock.h>
+#include <stdint.h>
#define CONFIG_SDRAM_BANK0
#ifdef CONFIG_SDRAM_BANK0
+/*
+ * According to the PPC405GPr Users Manual, only non-reserved
+ * bits of SDRAM registers can be set. This means reading the
+ * contents and masking off bits to be set.
+ */
+#define CMD_BITS 0x80C00000
+#define CMD_MASK 0xFFE00000
+#define TR_BITS 0x010E8016
+#define TR_MASK 0x018FC01F
+#define B0CR_BITS 0x00084001
+#define B0CR_MASK 0xFFCEE001
+#define RTR_BITS 0x08080000
+#define RTR_MASK 0xFFFF0000
+#define ECCCF_BITS 0x00000000
+#define ECCCF_MASK 0x00F00000
+#define PMIT_BITS 0x0F000000
+#define PMIT_MASK 0xFFC00000
+
+#define mfsdram0(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+#define set_sdram0(reg, val) \
+ mfsdram0(reg, reg32); \
+ reg32 &= ~(val##_MASK); \
+ reg32 |= (val##_BITS); \
+ mtsdram0(reg, reg32)
+
/*-----------------------------------------------------------------------
*/
void sdram_init(void)
{
+#if 0
unsigned long speed;
unsigned long sdtr1;
- unsigned long rtr;
+#endif
+ uint32_t reg32;
+#if 0
/*
* Determine SDRAM speed
*/
@@ -61,6 +90,7 @@ void sdram_init(void)
sdtr1 = 0x0086400d;
rtr = 0x05f00000;
}
+#endif
/*
* Disable memory controller.
@@ -69,31 +99,17 @@ void sdram_init(void)
//mtsdram0(mem_mcopt1, 0x00000000);
#if EMBEDDED_RAM_SIZE==128*1024*1024
- /*
- * Set MB0CF for bank 0. (0-128MB) Address Mode 3 since 13x10(4)
- */
- mtsdram0(mem_mb0cf, 0x000A4001);
-
- mtsdram0(mem_sdtr1, sdtr1);
- mtsdram0(mem_rtr, rtr);
+ /* TODO */
#elif EMBEDDED_RAM_SIZE==64*1024*1024
- /*
- * Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
- */
- mtsdram0(mem_mb0cf, 0x00084001);
-
- mtsdram0(mem_sdtr1, sdtr1);
- mtsdram0(mem_rtr, rtr);
+ set_sdram0(mem_sdtr1, TR);
+ set_sdram0(mem_mb0cf, B0CR);
+ set_sdram0(mem_rtr, RTR);
+ set_sdram0(mem_ecccf, ECCCF);
+ set_sdram0(mem_pmit, PMIT);
#elif EMBEDDED_RAM_SIZE==32*1024*1024
- /*
- * Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
- */
- mtsdram0(mem_mb0cf, 0x00062001);
+ /* TODO */
#elif EMBEDDED_RAM_SIZE==16*1024*1024
- /*
- * Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
- */
- mtsdram0(mem_mb0cf, 0x00046001);
+ /* TODO */
#endif
/*
@@ -106,7 +122,7 @@ void sdram_init(void)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
- mtsdram0(mem_mcopt1, 0x80800000);
+ set_sdram0(mem_mcopt1, CMD);
/*
* Wait for 10ms
diff --git a/src/mainboard/embeddedplanet/ep405pc/init.c b/src/mainboard/embeddedplanet/ep405pc/init.c
index b7da78eba4..240a392260 100644
--- a/src/mainboard/embeddedplanet/ep405pc/init.c
+++ b/src/mainboard/embeddedplanet/ep405pc/init.c
@@ -52,9 +52,9 @@ board_init(void)
mtebc(pb4ap, 0x04050000);
/*
- * Enable PCI
+ * Enable FLASH, NVRAM, POR
*/
- outb(0x80, 0xF4000001);
+ outb(0x9C, 0xF4000002);
/*
* Enable UART0
diff --git a/src/mainboard/motorola/sandpoint/Config.lb b/src/mainboard/motorola/sandpoint/Config.lb
index 12d840620b..53bc6a4c0e 100644
--- a/src/mainboard/motorola/sandpoint/Config.lb
+++ b/src/mainboard/motorola/sandpoint/Config.lb
@@ -53,11 +53,13 @@ end
## Include the secondary Configuration files
##
southbridge winbond/w83c553 end
-superio NSC/pc97307
- register "com1" = "{1}"
- register "lpt" = "{0}"
- register "port" = "TTYS0_BASE"
-end
+
+# Already intialized in board_init()
+#superio NSC/pc97307
+# register "com1" = "{1}"
+# register "lpt" = "{0}"
+# register "port" = "UART0_IO_BASE"
+#end
##
## Build the objects we have code for in this directory.
diff --git a/targets/embeddedplanet/ep405pc/Config.lb b/targets/embeddedplanet/ep405pc/Config.lb
index 991e9733e1..7f996390a0 100644
--- a/targets/embeddedplanet/ep405pc/Config.lb
+++ b/targets/embeddedplanet/ep405pc/Config.lb
@@ -13,7 +13,8 @@ uses CONFIG_CHIP_CONFIGURE
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BASE UART0_IO_BASE
+uses TTYS0_BASE TTYS0_BAUD TTYS0_DIV
+uses UART0_IO_BASE
uses NO_POST
uses CONFIG_IDE_STREAM
uses CONFIG_SYS_CLK_FREQ
@@ -51,6 +52,9 @@ option NO_POST=1
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BASE={UART0_IO_BASE}
+# Divisor of 69 == 9600 baud due to weird clocking
+option TTYS0_DIV=69
+option TTYS0_BAUD=9600
## Boot linux from IDE
option CONFIG_IDE_STREAM=1